FLOW PINNING IN A SERVER ON A CHIP

• US 20150324306A1
• Filed: 01/24/2014
• Published: 11/12/2015
• Est. Priority Date: 01/24/2014
• Status: Active Grant

• Current Assignee: Ampere Computing LLC
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Chudgar, Keyur, Sankaran, Kumar
• Granted Patent: US 9,588,923 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.

Claims

1. A server on a chip, comprising:

a first data structure, executed by a processor, configured for extracting a metadata string from a packet;

a second data structure, executed by the processor, configured for associating the packet with a result database based on the metadata string; and

an Ethernet direct memory access engine configured for assigning the packet to a queue based on the result database, wherein the queue is associated with a respective core of a multiprocessor.

2. The server on a chip of claim 1, wherein the data structure is a patricia tree.

3. The server on a chip of claim 1, wherein the second data structure is an AVL search tree.

4. The server on a chip of claim 1, wherein the metadata string comprises a source internet protocol address, a destination internet protocol address, a source port, and a destination port.

5. The server on a chip of claim 1, wherein the metadata string is a 12 byte long string that contains 4 items of information.

6. The server on a chip of claim 1, wherein the metadata string is extracted from layer 3 and layer 4 header data of the packet.

7. The server on a chip of claim 1, wherein the second data structure associates the packet with the associated result database based on indexing a lookup table with the metadata string.

8. The server on a chip of claim 1, further comprising a queue manager configured for issuing an interrupt to cores of the multiprocessor, wherein the queue issues an interrupt to the respective core.

9. The server on a chip of claim 1, wherein the first data structure extracts a plurality of metadata strings from a plurality of packets.

10. The server on a chip of claim 1, wherein the first data structure is preprogrammed to extract the metadata string based on the second data structure.

11. The server on a chip of claim 1, wherein the Ethernet direct memory access engine is further configured for copying the packet to a free buffer pool based on the result database.

12. The server on a chip of claim 11, wherein the Ethernet direct memory access engine is further configured for enqueuing a descriptor message to a queue, wherein the descriptor message is based on the packet and the free buffer pool.

13. A computer implemented method for performing flow pinning of a packet stream to a core of a multiprocessor, comprising:

extracting, by a processor executing a first data structure, a metadata string from a packet;

associating, by the processor executing a second data structure, the packet with a respective result database based on the metadata string; and

assigning, by an Ethernet direct memory access engine, the packet to a queue based on the result database, wherein the queue is associated with a respective core of multiprocessor.

14. The computer implemented method of claim 13, wherein the extracting further comprises extracting a 12 byte long string using a patricia tree, wherein the string comprises a source Internet protocol address, a destination internet protocol address, a source port, and a destination port.

15. The computer implemented method of claim 13, wherein the extracting further comprises extracting the metadata string from layer 3 and layer 4 header data of the packet.

16. The computer implemented method of claim 13, wherein the associating further comprises associating the packet with the associated result database based on indexing a lookup table with the metadata string.

17. The computer implemented method of claim 13, further comprising issuing an interrupt to the respective core via the assigned queue.

18. The computer implemented method of claim 13, wherein the extracting further comprises extracting a plurality of metadata strings from a plurality of packets.

19. The computer implemented method of claim 13, wherein the extracting further comprises extracting a plurality of metadata strings from a plurality of packets. copying the packet to a free buffer pool based on the result database;

and enqueuing a descriptor message to a queue, wherein the descriptor message is based on the copied packet and a predetermined buffer.

20. A server on a chip, comprising:

means for extracting a metadata string from a packet;

means for associating the packet with a respective core of a multiprocessor based on the metadata string; and

means for assigning the packet to a queue associated with the processor.