THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF
First Claim
1. A method of manufacturing a thin film transistor array panel, the method comprising:
- forming a gate electrode on an insulation substrate;
forming a gate insulating layer on the gate electrode;
forming a semiconductor pattern on the gate insulating layer;
forming an etch stopper intersecting and overlapping the semiconductor pattern on the semiconductor pattern; and
treating an exposed portion of the semiconductor pattern, thereby forming a source region and a drain region in the exposed portion of the semiconductor pattern,wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of a channel region, the channel region being a portion of the semiconductor pattern covered by the etch stopper.
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Abstract
The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.
10 Citations
18 Claims
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1. A method of manufacturing a thin film transistor array panel, the method comprising:
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forming a gate electrode on an insulation substrate; forming a gate insulating layer on the gate electrode; forming a semiconductor pattern on the gate insulating layer; forming an etch stopper intersecting and overlapping the semiconductor pattern on the semiconductor pattern; and treating an exposed portion of the semiconductor pattern, thereby forming a source region and a drain region in the exposed portion of the semiconductor pattern, wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of a channel region, the channel region being a portion of the semiconductor pattern covered by the etch stopper. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of manufacturing a thin film transistor array panel, the method comprising:
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forming a semiconductor pattern comprising an oxide semiconductor on an insulation substrate; depositing an insulating material on the semiconductor pattern to form an insulating material layer; forming a gate electrode on the insulating material layer; patterning the insulating material layer by using the gate electrode as an etching mask to form a gate insulating layer and to expose a portion of the semiconductor pattern; and treating the exposed semiconductor pattern to form a channel region covered by the gate electrode, and to form a source region and a drain region facing each other with respect to the channel region, wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region. - View Dependent Claims (17, 18)
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Specification