TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

• US 20150341052A1
• Filed: 05/19/2015
• Published: 11/26/2015
• Est. Priority Date: 05/21/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JEONG, Hong-sil, KIM, Kyung-joong, MYUNG, Se-ho, MOUHOUCHE, Belkacem, LOBETE, Daniel Ansorregui
• Granted Patent: US 9,602,245 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/253 with concatenated codes
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/2707 Simple row-column interleaver, i.e. pure block interleaving
• CPC Class Codes: H03M 13/271 Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
• CPC Class Codes: H03M 13/2778 Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
• CPC Class Codes: H03M 13/2792 Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 27/36 Modulator circuits; Transmitter circuits

Abstract

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Claims

1. A transmitting apparatus comprising:

an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits;

an interleaver configured to interleave the LDPC codeword; and

a modulator configured to map the interleaved LDPC codeword onto a modulation symbol,

wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

2. The transmitting apparatus of claim 1, wherein the parity check matrix comprises an information word submatrix and a parity submatrix,

wherein each of the plurality of bit groups constituting the LDPC codeword is formed of M number of bits,

wherein M is a common divisor of N_ldpc and K_ldpc and is determined to satisfy Q_ldpc=(N_ldpc−

K_ldpc)/M, and

wherein Q_ldpc is a cyclic shift parameter value regarding columns in a column group of the information word submatrix of the parity check matrix, N_ldpc is a length of the LDPC codeword, and K_ldpc is a length of the information word bits of the LDPC codeword.

3. The transmitting apparatus of claim 1, wherein the interleaver comprises:

a group interleaver configured to divide the LDPC codeword into the plurality of bit groups and rearrange an order of the plurality of bit groups in bit group wise; and

a block interleaver configured to interleave the plurality of bit groups the order of which is rearranged.

4. The transmitting apparatus of claim 3, further comprising a parity interleaver configured to interleave parity bits of the LDPC codeword,

wherein the group interleaver is configured to divide the LDPC codeword, of which the parity bits are interleaved, into the plurality of bit groups and rearrange an order of the plurality of bit groups in bit group wise.

5. The transmitting apparatus of claim 3, wherein the group interleaver is configured to rearrange the order of the plurality of bit groups in bit group wise by using the following equation:

Y_j=X<sub>π

(j)</sub>(0≦

j<

N_group),

where X_j is a j^th bit group before the plurality of bit groups are interleaved, Y_j is a j^th bit group after the plurality of bit groups are interleaved, N_group is a total number of the plurality of bit groups, and π

(j) is a parameter indicating an order of the interleaving by the group interleaver.

6. The transmitting apparatus of claim 5, wherein π

(j) is determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

7. The transmitting apparatus of claim 5, wherein the π

(j), when the LDPC codeword has a length of 16200, a modulation method is 256-QAM, and a code rate is 5/15, is defined as a table below;

8. The transmitting apparatus of claim 3, wherein the block interleaver is configured to interleave by writing bits included in the plurality of bit groups in a plurality of columns in bit group wise in a column direction, and reading the plurality of columns, in which the bits included in the plurality of bit groups are written in bit group wise, in a row direction.

9. The transmitting apparatus of claim 8, wherein the block interleaver is configured to serially write, in the plurality of columns, bits included in at least some bit groups which are writable in the plurality of columns in bit group wise from among the plurality of bit groups, and

wherein the block interleaver is further configured to divide bits included in bit groups other than the at least some bit groups in an area which is different from an area where the at least some bit groups are written in the plurality of columns in bit group wise.

10. The transmitting apparatus of claim 9, wherein the block interleaver is configured to divide the plurality of columns, each comprising a plurality of rows, into a first part and a second part, and

wherein the block interleaver is further configured to write bits included in at least some bit groups in the first part such that bits included in a same bit group is written in a same column, and write bits included in at least one bit group other than the at least some bit groups in the second part.

11. The transmitting apparatus of claim 10, wherein the block interleaver is configured to divide the plurality of columns into the first and second parts based on at least one of a number of the columns, a number of the bit groups constituting the LDPC codeword, and a number of bits constituting each of the bit groups.

12. The transmitting apparatus of claim 10, wherein, if a number of bit groups constituting the LDPC codeword is an integer multiple of a number of the columns, the block interleaver is configured to write all bits included in the bit groups serially in the plurality of columns without dividing the plurality of columns into the first and second parts.

13. An interleaving method of a transmitting apparatus, comprising:

performing a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits;

interleaving the LDPC codeword; and

mapping the interleaved LDPC codeword onto a modulation symbol,

wherein the mapping comprises mapping a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

14. The interleaving method of claim 13, wherein the parity check matrix comprises an information word submatrix and a parity submatrix,

wherein each of the plurality of bit groups constituting the LDPC codeword is formed of M number of bits,

wherein M is a common divisor of N_ldpc and K_ldpc and is determined to satisfy Q_ldpc=(N_ldpc−

K_ldpc)/M, and

wherein Q_ldpc is a cyclic shift parameter value regarding columns in a column group of the information word submatrix of the parity check matrix, N_ldpc is a length of the LDPC codeword, and K_ldpc is a length of the information word bits of the LDPC codeword.

15. The interleaving method of claim 13, wherein the interleaving comprises:

dividing the LDPC codeword into the plurality of bit groups and rearranging an order of the plurality of bit groups in bit group wise; and

interleaving the plurality of bit groups of which an order is rearranged.

16. The interleaving method of claim 15, further comprising interleaving parity bits of the LDPC codeword,

wherein the LDPC codeword, of which the parity bits are interleaved, are divided into the plurality of bit groups for the rearranging an order of the plurality of bit groups in bit group wise.

17. The interleaving method of claim 13, wherein the rearranging in bit group wise comprises rearranging the order of the plurality of bit groups in bit group wise by using the following equation:

Y_j=X<sub>π

(j)</sub>(0≦

j<

N_group),

where x, is a j^th bit group before the plurality of bit groups are interleaved, Y_j is a j^th bit group after the plurality of bit groups are interleaved, N_group is a total number of the plurality of bit groups, and π

(j) is a parameter indicating an order of the interleaving by the group interleaver.

18. The interleaving method of claim 17, wherein π

(j) is determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate.

19. The method of claim 17, wherein the π

(j), when a length of the LDPC codeword is 16200, a modulation method is 256-QAM, and a code rate is 5/15, is defined as a table below;

20. The method of claim 15, wherein the interleaving the plurality of bit groups comprises interleaving by writing bits included in the plurality of bit groups in a plurality of columns in bit group wise in a column direction, and reading the plurality of columns, in which the bits included in the plurality of bit groups are written in bit group wise, in a row direction.