WELL RESISTORS AND POLYSILICON RESISTORS

• US 20150349046A1
• Filed: 05/27/2014
• Published: 12/03/2015
• Est. Priority Date: 05/27/2014
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Heinrich-Barna, Stephen Keith, Verret, Douglas P., Tsao, Alwin J.
• Granted Patent: US 9,202,859 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66166 Resistors with PN junction
• CPC Class Codes: H01L 29/8605 Resistors with PN junctions

Abstract

An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Claims

1. An integrated circuit, comprising:

a substrate comprising semiconductor material at a top surface of the substrate;

field oxide formed by a shallow trench isolation (STI) process disposed at the top surface of the substrate;

a well resistor disposed in the semiconductor material under the field oxide;

resistor head active areas disposed through the field oxide proximate to ends of the well resistor; and

resistor dummy active areas disposed through the field oxide in an area for the well resistor, the resistor dummy active areas being free of electrical connections above the substrate, the resistor dummy active areas having a density of 10 percent to 80 percent.

2. The integrated circuit of claim 1, wherein the resistor dummy active areas have a density of 20 percent to 50 percent.

3. The integrated circuit of claim 1, further comprising heavily doped dummy diffused regions in the resistor dummy active areas, the heavily doped dummy diffused regions having an average doping density at least ten times an average doping density in the well resistor.

4. The integrated circuit of claim 3, wherein the heavily doped dummy diffused regions have a same conductivity type as the well resistor.

5. The integrated circuit of claim 1, further comprising metal silicide layers on top surfaces of the resistor head active areas and the resistor dummy active areas.

6. The integrated circuit of claim 1, wherein the resistor dummy active areas are configured as a plurality of rectangles such that each the rectangle extends from proximate to one side of the well resistor to proximate to an opposite side of the well resistor.

7. A method of forming an integrated circuit, comprising the steps:

providing a substrate comprising semiconductor material at a top surface of the substrate;

forming a chemical mechanical polish (CMP) stop layer over the substrate;

forming an STI mask over the CMP stop layer, the STI mask covering areas for active areas of the integrated circuit, the active areas including resistor head active areas in an area for a well resistor and including resistor dummy active areas in the area for the well resistor, the resistor dummy active areas having a density of 10 percent to 80 percent;

removing the CMP stop layer and removing a portion of the semiconductor material of the substrate in areas exposed by the STI mask to form STI trenches 250 nanometers to 500 nanometers deep in the substrate;

forming a layer of trench fill dielectric material in the STI trenches and over the CMP stop layer over the active areas, the trench fill dielectric material filling the STI trenches;

planarizing the trench fill dielectric material down to the CMP stop layer by a CMP process, wherein the CMP process removes all of the trench fill dielectric material from over the CMP stop layer and does not remove any of the semiconductor material from the resistor head active areas and the resistor dummy active areas;

removing a remaining portion of the CMP stop layer wherein the trench fill dielectric material in the STI trenches forms field oxide of the integrated circuit;

implanting well dopants through the field oxide into the semiconductor material of the substrate under the field oxide in the area for the well resistor;

heating the substrate in a well anneal process to activate the well dopants to form the well resistor; and

forming contacts to provide electrical connections to the well resistor through the resistor head active areas, wherein the resistor dummy active areas are free of electrical connections above the substrate.

8. The method of claim 7, wherein the resistor dummy active areas have a density of 20 percent to 50 percent.

9. The method of claim 7, further comprising the steps:

forming a dummy region implant mask over the substrate and the field oxide so as to expose the resistor dummy active areas;

implanting source/drain dopants into the resistor dummy active areas while the dummy region implant mask is in place;

subsequently removing the dummy region implant mask; and

performing an anneal operation to activate the source/drain dopants to form heavily doped dummy diffused regions in the resistor dummy active areas, the heavily doped dummy diffused regions having an average doping density at least ten times an average doping density in the well resistor.

10. The method of claim 9, wherein the heavily doped dummy diffused regions have a same conductivity type as the well resistor.

11. The method of claim 7, further comprising the steps:

forming a layer of refractory metal on top surfaces of the resistor head active areas and the resistor dummy active areas;

heating the substrate to form layers of metal silicide at the top surfaces of the resistor head active areas and the resistor dummy active areas; and

subsequently removing unreacted refractory metal from the layer of refractory metal.

12. The method of claim 7, wherein the resistor dummy active areas are configured as a plurality of rectangles such that each the rectangle extends from proximate to one side of the well resistor to proximate to an opposite side of the well resistor.

13. An integrated circuit, comprising:

a substrate comprising semiconductor material at a top surface of the substrate;

field oxide formed by an STI process disposed at the top surface of the substrate;

a polysilicon resistor disposed over the field oxide, the polysilicon resistor formed from a layer of CMP-planarized polysilicon; and

resistor dummy active areas disposed through the field oxide in an area for the polysilicon resistor, the resistor dummy active areas being free of electrical connections above the substrate, the resistor dummy active areas having a density of 10 percent to 80 percent.

14. The integrated circuit of claim 13, wherein the resistor dummy active areas do not extend under the polysilicon resistor.

15. The integrated circuit of claim 13, wherein the resistor dummy active areas extend under the polysilicon resistor, being separated from the polysilicon resistor by a dielectric layer at top surfaces of the resistor dummy active areas.

16. The integrated circuit of claim 13, wherein the resistor dummy active areas have a density of 20 percent to 50 percent.

17. A method of forming an integrated circuit, comprising the steps:

providing a substrate comprising semiconductor material at a top surface of the substrate;

forming a CMP stop layer over the substrate;

forming an STI mask over the CMP stop layer, the STI mask covering areas for active areas of the integrated circuit, the active areas including resistor dummy active areas in the area for a polysilicon resistor, the resistor dummy active areas having a density of 10 percent to 80 percent;

removing the CMP stop layer and removing a portion of the semiconductor material of the substrate in areas exposed by the STI mask to form STI trenches 250 nanometers to 500 nanometers deep in the substrate;

forming a layer of trench fill dielectric material in the STI trenches and over the CMP stop layer over the active areas, the trench fill dielectric material filling the STI trenches;

planarizing the trench fill dielectric material down to the CMP stop layer by a CMP process, wherein the CMP process removes all of the trench fill dielectric material from over the CMP stop layer and does not remove any of the semiconductor material from the resistor dummy active areas;

removing a remaining portion of the CMP stop layer wherein the trench fill dielectric material in the STI trenches forms field oxide of the integrated circuit;

forming a layer of polysilicon over the field oxide and the resistor dummy active areas;

planarizing the layer of polysilicon using a CMP process to form a CMP-planarized polysilicon layer;

forming a polysilicon etch mask over the CMP-planarized polysilicon layer which defines the polysilicon resistor;

removing polysilicon from the CMP-planarized polysilicon layer in areas outside the polysilicon etch mask to form the polysilicon resistor; and

forming contacts to provide electrical connections to the polysilicon resistor, wherein the resistor dummy active areas are free of electrical connections above the substrate.

18. The method of claim 17, wherein the resistor dummy active areas do not extend under the polysilicon resistor.

19. The method of claim 17, wherein the resistor dummy active areas extend under the polysilicon resistor, being separated from the polysilicon resistor by a dielectric layer at top surfaces of the resistor dummy active areas.

20. The method of claim 17, wherein the resistor dummy active areas have a density of 20 percent to 50 percent.