INTEGRATED INTERPOSER SOLUTIONS FOR 2D AND 3D IC PACKAGING

• US 20150357272A1
• Filed: 12/30/2014
• Published: 12/10/2015
• Est. Priority Date: 06/04/2014
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Shen, Hong, Woychik, Charles G., Sitaram, Arkalgud R., Gao, Guilian
• Granted Patent: US 9,741,649 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92225 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/162 : the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/167 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/16788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

Claims

1. An integrated circuit (IC) package, comprising:

a first substrate having a backside surface and a top surface with a cavity disposed therein, the cavity having a floor defining a front side surface;

a plurality of first electroconductive contacts disposed on the front side surface;

a plurality of second electroconductive contacts disposed on the back side surface;

a plurality of first electroconductive elements penetrating through the first substrate and coupling selected ones of the first and second electroconductive contacts to each other;

a first die containing an IC electroconductively coupled to corresponding ones of the first electroconductive contacts;

a second substrate having a bottom surface sealingly attached to the top surface of the first substrate; and

a dielectric material disposed in the cavity and encapsulating the first die.

2. The IC package of claim 1, further comprising:

a plurality of third electroconductive contacts disposed on a top surface of the first die;

a plurality of fourth electroconductive contacts disposed on a top surface of the second substrate;

a plurality of second electroconductive elements penetrating through the second substrate and coupling selected ones of the third and fourth electroconductive contacts to each other;

a second die containing an IC electroconductively coupled to corresponding ones of the fourth electroconductive contacts; and

a cover having a bottom surface sealingly attached to the top surface of the second substrate and enclosing the second die.

3. The IC package of claim 2, wherein the cover comprises a polymer molded over the top surface of the second substrate and encapsulating the second die.

4. The IC package of claim 2, wherein the cover comprises:

a third substrate having a bottom surface with a cavity disposed therein, the bottom surface being sealingly attached to the top surface of the second substrate such that the second die is disposed within the cavity; and

a dielectric material disposed within the cavity and encapsulating the second die.

5. The IC package of claim 4, wherein the dielectric material comprises an inorganic material.

6. The IC package of claim 4, wherein at least one of the first, second and/or third substrates comprises a semiconductor.

7. The IC package of claim 2, further comprising an electroconductive redistribution layer (RDL) disposed on at least one of the front side surface of the first substrate, the back side surface of the first substrate and/or the top surface of the second substrate and coupling selected ones of the electroconductive contacts respectively disposed thereon to each other.

8. The IC package of claim 2, wherein at least one of the electroconductive elements penetrating through the first and second substrates comprises a through-silicon via (TSV).

9. The IC package of claim 2, wherein at least one of the first and second dies is electroconductively coupled to the corresponding ones of the electroconductive contacts by solder bumps.

10. The IC package of claim 2, wherein the first die, the second die or both the first and the second die comprises a plurality of dies.

11. A method for making an integrated circuit (IC) package, the method comprising:

providing a first substrate having a backside surface, a top surface and a cavity disposed in the top surface, the cavity having a floor defining a front side surface;

forming electroconductive contacts on respective ones of the front and back side surfaces;

forming a plurality of electroconductive elements penetrating through the first substrate and interconnecting selected ones of the electroconductive contacts respectively disposed on the front and back side surfaces to each other;

disposing a first die containing an IC within the cavity and eleetroconductively coupling it to corresponding ones of the electroconductive contacts disposed on the front side surface;

sealingly attaching a bottom surface of a second substrate to the top surface of the first substrate; and

injecting a dielectric material into the cavity so as to encapsulate the first die.

12. The method of claim 11, further comprising etching a top surface of the first die and the top surface of the first substrate to reduce a final thickness of the IC package.

13. The method of claim 11, further comprising:

coupling the back side surface of the first substrate to a wafer chuck; and

grinding top surfaces of the dielectric material, the die and the first substrate to make them coplanar with each other and to reduce a final thickness of the IC package.

14. The method of claim 11, further comprising:

coupling a top surface of the second substrate to a wafer chuck; and

grinding the back side surface of the first substrate to reduce a final thickness of the IC package.

15. The method of claim 11, wherein the forming of the electroconductive elements comprises reactive ion etching (RIE).

16. An integrated circuit (IC) package, comprising:

a first substrate having a backside surface and a front side surface;

a plurality of electroconductive elements penetrating through the first substrate and coupling selected ones of electroconductive contacts respectively disposed on the front side surface and the back side surface to each other;

at least one first die containing an IC electroconductively coupled to corresponding ones of the electroconductive elements disposed on the front side surface;

a second substrate having a bottom surface sealingly attached to the front side surface of the first substrate and a through-opening surrounding the first die;

a third substrate having a bottom surface sealingly attached to a top surface of the second substrate, the bottom surface and the through-opening defining a first cavity enclosing the first die, and

a dielectric material disposed within the first cavity and encapsulating the at least one first die.

17. The IC package of claim 16, further comprising:

a plurality of electroconductive elements penetrating through the third substrate and coupling selected ones of electroconductive contacts respectively disposed on a top surface of the at least one first die and a top surface of the third substrate to each other;

at least one second die containing an IC electroconductively coupled to corresponding ones of the electroconductive contacts disposed on the top surface of the third substrate; and

a dielectric material encapsulating the at least one second die.

18. The IC package of claim 17, wherein

the third substrate includes a second cavity in the bottom surface thereof, and

the at least one second die and the dielectric material are disposed within the second cavity.

19. The IC package of claim 18, wherein the dielectric material comprises an inorganic material.

20. The IC package of claim 17, further comprising an electroconductive redistribution layer (RDL) disposed on at least one of the front side surface of the first substrate, the back side surface of the first substrate and/or the top surface of the third substrate and coupling selected ones of the electroconductive contacts respectively disposed thereon to each other.

21. The IC package of claim 17, wherein at least one of the at least one first die and the at least one second die is electroconductively coupled to the corresponding ones of the electroconductive contacts by solder bumps.

22. An integrated circuit (IC) package, comprising:

a first substrate having a back side surface and a front side surface, each of the back side and front side surfaces having an associated plurality of electroconductive contacts respectively disposed thereon;

a plurality of electroconductive elements penetrating through the first substrate and coupling selected ones of the associated electroconductive contacts respectively disposed on the front side surface and the back side surface to each other;

a first die containing an IC electroconductively coupled to corresponding ones of the electroconductive contacts disposed on the front side surface;

a second substrate having a cavity disposed in a bottom surface thereof, the bottom surface being sealingly attached to the front side surface of the first substrate such that the cavity encloses the first die; and

a dielectric material disposed in the cavity and encapsulating the first die.

23. The IC package of claim 22, further comprising an electroconductive redistribution layer (RDL) disposed on the front side surface of the first substrate and coupling selected ones of the electroconductive contacts disposed thereon to each other.

24. The IC package of claim 22, wherein the dielectric material comprises an inorganic material.