SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

• US 20150364473A1
• Filed: 08/21/2015
• Published: 12/17/2015
• Est. Priority Date: 05/11/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ju-Youn, Seo, Kwang-You
• Granted Patent: US 9,627,380 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.

Claims

1. A semiconductor device comprising:

a substrate;

a first interlayer insulating film disposed in a first region of the substrate and including a first trench;

a second interlayer insulating film disposed in a second region of the substrate and including a second trench;

a first gate insulating film formed along sidewalls and a bottom surface of the first trench;

a second gate insulating film formed along sidewalls and a bottom surface of the second trench;

at least one first work function adjusting film disposed in the first trench, and disposed on or above sidewalls and a bottom surface of the first gate insulating film, each of side portions of the at least one first work function adjusting film having a chamfered top surface, the side portions of the at least one first work function adjusting film being disposed on the sidewalls of the first gate insulating film;

at least one second work function adjusting film disposed in the second trench, and disposed on or above sidewalls and a bottom surface of the second gate insulating film, each of side portions of the at least one second work function adjusting film having a chamfered top surface, the side portions of the at least one second work function adjusting film being disposed on the sidewalls of the second gate insulating film;

a first adhesive film disposed in the first trench, and disposed on sidewalls and a bottom surface of the at least one first work function adjusting film;

a second adhesive film disposed in the second trench, and disposed on sidewalls and a bottom surface of the at least one second work function adjusting film;

a first metal gate pattern disposed on the first adhesive film and filling the first trench; and

a second metal gate pattern disposed on the second adhesive film and filling the second trench,

wherein the first adhesive film is further disposed on the chamfered top surface of each of the side portions of the at least one first work function adjusting film, and

the second adhesive film is further disposed on the chamfered top surface of each of the side portions of the at least one second work function adjusting film.

2. The semiconductor device of claim 1, wherein a distance between a surface of the first metal gate pattern and a bottom surface of the first adhesive film is greater than a distance between a surface of the second metal gate pattern and a bottom surface of the second adhesive film.

3. The semiconductor device of claim 1, wherein an N type transistor is formed in the first region of the substrate, and a P type transistor is formed in the second region of the substrate.

4. The semiconductor device of claim 1, wherein the at least one second work function adjusting film includes a P type work function adjusting film and an N type work function adjusting film formed on the P type work function adjusting film.

5. The semiconductor device of claim 4, wherein the P type work function adjusting film and the second adhesive film are made of the same material.

6. The semiconductor device of claim 4, wherein the P type work function adjusting film and the second adhesive film are made of titanium nitride (TiN).

7. The semiconductor device of claim 1, wherein the at least one first work function adjusting layer includes an N type work function adjusting film.

8. The semiconductor device of claim 7, wherein the N type work function adjusting film is made of a material selected from the group consisting of TiAl, TiAlN, TaC, TiC and HfSi.

9. The semiconductor device of claim 1, wherein each of the first gate insulating film and the second gate insulting film includes a high-k dielectric material.

10. The semiconductor device of claim 1, wherein a width of the first metal gate pattern is greater than a width of the second metal gate pattern

11. The semiconductor device of claim 1, further comprising:

a first etch stop film disposed between the first gate insulating film and the at least one first work function adjusting film; and

a second etch stop film disposed between the second gate insulating film and the at least one second work function adjusting film.

12. A semiconductor device comprising:

a substrate;

a first interlayer insulating film disposed in a first region of the substrate and including a first trench;

a second interlayer insulating film disposed in a second region of the substrate and including a second trench;

a first gate insulating film formed along sidewalls and a bottom surface of the first trench;

a second gate insulating film formed along sidewalls and a bottom surface of the second trench;

at least one first work function adjusting film disposed in the first trench, and disposed on or above sidewalls and a bottom surface of the first gate insulating film, each of side portions of the at least one first work function adjusting film having a chamfered top surface, the side portions of the at least one first work function adjusting film being disposed on the sidewalls of the first gate insulating film;

at least one second work function adjusting film disposed in the second trench, and disposed on or above sidewalls and a bottom surface of the second gate insulating film, each of side portions of the at least one second work function adjusting film having a chamfered top surface, the side portions of the at least one second work function adjusting film being disposed on the sidewalls of the second gate insulating film;

a first adhesive film disposed in the first trench, and disposed on sidewalls and a bottom surface of the at least one first work function adjusting film;

a second adhesive film disposed in the second trench, and disposed on sidewalls and a bottom surface of the at least one second work function adjusting film;

a first metal gate pattern disposed on the first adhesive film and filling the first trench; and

a second metal gate pattern disposed on the second adhesive film and filling the second trench,

wherein a width of a bottom portion of the first metal gate pattern is greater than a width of a bottom portion of the second metal gate pattern.

13. The semiconductor device of claim 12, wherein the first adhesive film is further disposed on the chamfered top surface of each of the side portions of the at least one first work function adjusting film, and

the second adhesive film is further disposed on the chamfered top surface of each of the side portions of the at least one second work function adjusting film.

14. The semiconductor device of claim 12, wherein a distance between a surface of the first metal gate pattern and a bottom surface of the first adhesive film is greater than a distance between a surface of the second metal gate pattern and a bottom surface of the second adhesive film.

15. The semiconductor device of claim 12, wherein an N type transistor is formed in the first region of the substrate, and a P type transistor is formed in the second region of the substrate.

16. The semiconductor device of claim 12, wherein the semiconductor device is a fin type transistor.

17. A semiconductor device comprising:

a substrate including a fin;

a gate electrode formed on the fin; and

a source/drain disposed at two sides of the gate electrode,

wherein the gate electrode includes;

a first interlayer insulating film disposed in a first region of the substrate and including a first trench;

a second interlayer insulating film disposed in a second region of the substrate and including a second trench;

a first gate insulating film formed along sidewalls and a bottom surface of the first trench;

a second gate insulating film formed along sidewalls and a bottom surface of the second trench;

at least one first work function adjusting film disposed in the first trench, and disposed on or above sidewalls and a bottom surface of the first gate insulating film, each of side portions of the at least one first work function adjusting film having a chamfered top surface, the side portions of the at least one first work function adjusting film being disposed on the sidewalls of the first gate insulating film;

at least one second work function adjusting film disposed in the second trench, and disposed on or above sidewalls and a bottom surface of the second gate insulating film, each of side portions of the at least one second work function adjusting film having a chamfered top surface, the side portions of the at least one second work function adjusting film being disposed on the sidewalls of the second gate insulating film;

a first adhesive film disposed in the first trench, and disposed on sidewalls and a bottom surface of the at least one first work function adjusting film; and

a second adhesive film disposed in the second trench, and disposed on sidewalls and a bottom surface of the at least one second work function adjusting film,

wherein a shortest distance between the fin and the first adhesive film is less than a shortest distance between the fin and the second adhesive film.

18. The semiconductor device of claim 17, further comprising:

a first metal gate pattern disposed on the first adhesive film and filling the first trench; and

a second metal gate pattern disposed on the second adhesive film and filling the second trench.

19. The semiconductor device of claim 17, wherein the first adhesive film is further disposed on the chamfered top surface of each of the side portions of the at least one first work function adjusting film, and

the second adhesive film is further disposed on the chamfered top surface of each of the side portions of the at least one second work function adjusting film.

20. The semiconductor device of claim 17, wherein the fin includes an epitaxial layer.