LATENT MODIFICATION INSTRUCTION FOR TRANSACTIONAL EXECUTION

• US 20150378732A1
• Filed: 06/30/2014
• Published: 12/31/2015
• Est. Priority Date: 06/30/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gschwind, Michael Karl, Salapura, Valentina, Shum, Chung-Lung K., Slegel, Timothy J.
• Granted Patent: US 9,600,286 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/466 Transaction processing
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

An instruction stream includes a transactional code region. The transactional code region includes a latent modification instruction (LMI), a next sequential instruction (NSI) following the LMI, and a set of target instructions following the NSI in program order. Each target instruction has an associated function, and the LMI at least partially specifies a substitute function for the associated function. A processor executes the LMI, the NSI, and at least one of the target instructions, employing the substitute function at least partially specified by the LMI. The LMI, the NSI, and the target instructions may be executed by the processor in sequential program order or out of order.

Claims

1-6. -6. (canceled)

7. A computer system for processing transactions in a computing environment with transactional memory, the computer system comprising:

a memory; and

a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising;

executing, by a processor, a latent modification instruction (LMI) within the transaction, the transaction comprising a set of target instructions following the LMI in program order in an instruction stream, each of the target instructions having an associated function, the LMI at least partially specifying a substitute function to be substituted for the associated function; and

executing, by the processor, a next sequential instruction (NSI) and at least one of the target instructions within the transaction, the NSI following the LMI in program order in the instruction stream, wherein the executing the at least one of the target instructions employs the substitute function at least partially specified by the LMI.

8. The system of claim 7, wherein the LMI, the NSI, and the at least one of the target instructions are executed by the processor in consecutive program order.

9. The system of claim 7, wherein an operand associated with the LMI specifies a number of target instructions in the set of target instructions.

10. The system of claim 7, wherein a postfix instruction follows the set of target instructions in program order in the instruction stream.

11. The system of claim 7, wherein the substitute function at least partially specified by the LMI affects cache coherency of the target instructions, and wherein the method further comprises:

obtaining exclusive ownership of cache lines affected by load operations of the target instructions.

12. The system of claim 7, wherein the set of target instructions includes a second part of a combination instruction, wherein the LMI is a first part of the combination instruction, wherein the function of the second part of the combination instruction is a null function, and wherein the first part of the combination instruction and the second part of the combination instruction combine to specify the substitute function.

13. The system of claim 7, wherein the transaction is associated with a pre-transaction architectural state, wherein the set of target instructions includes a last target instruction, and wherein the method further comprises:

executing, before executing the last target instruction, a transactional abort in response to an interrupt while processing the transaction, the transactional abort restoring the pre-transaction architectural state.

14. A computer program product for processing transactions in a computing environment with transactional memory, the computer program product comprising:

a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising;

executing, by a processor, a latent modification instruction (LMI) within the transaction, the transaction comprising a set of target instructions following the LMI in program order in an instruction stream, each of the target instructions having an associated function, the LMI at least partially specifying a substitute function to be substituted for the associated function; and

executing, by the processor, a next sequential instruction (NSI) and at least one of the target instructions within the transaction, the NSI following the LMI in program order in the instruction stream, wherein the executing the at least one of the target instructions employs the substitute function at least partially specified by the LMI.

15. The computer program product of claim 14, wherein the LMI, the NSI, and the at least one of the target instructions are executed by the processor in consecutive program order.

16. The computer program product of claim 14, wherein an operand associated with the LMI specifies a number of target instructions in the set of target instructions.

17. The computer program product of claim 14, wherein a postfix instruction follows the set of target instructions in program order in the instruction stream.

18. The computer program product of claim 14, wherein the substitute function at least partially specified by the LMI affects cache coherency of the target instructions, and wherein the method further comprises:

obtaining exclusive ownership of cache lines affected by load operations of the target instructions.

19. The computer program product of claim 14, wherein the set of target instructions includes a second part of a combination instruction, wherein the LMI is a first part of the combination instruction, wherein the function of the second part of the combination instruction is a null function, and wherein the first part of the combination instruction and the second part of the combination instruction combine to specify the substitute function.

20. The computer program product of claim 14, wherein the transaction is associated with a pre-transaction architectural state, wherein the set of target instructions includes a last target instruction, and wherein the method further comprises:

executing, before executing the last target instruction, a transactional abort in response to an interrupt while processing the transaction, the transactional abort restoring the pre-transaction architectural state.