METHODS OF FORMING PRINTABLE INTEGRATED CIRCUIT DEVICES AND DEVICES FORMED THEREBY

• US 20150380436A1
• Filed: 05/11/2015
• Published: 12/31/2015
• Est. Priority Date: 03/26/2009
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: Semprius, Inc.
• Inventors: Bower, Christopher, Meitl, Matthew, Carr, Joseph, Menard, Etienne
• Granted Patent: US 9,443,883 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate

Abstract

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

Claims

1-18. -18. (canceled)

19. A wafer of integrated circuit devices, comprising:

a substrate;

a plurality of integrated circuits, each integrated circuit comprising a semiconductor active layer;

one or more multi-layer electrical interconnect networks, each multi-layer electrical interconnect network disposed on the semiconductor active layer of a corresponding integrated circuit;

a plurality of anchors disposed on the substrate, each anchor disposed adjacent to at least one integrated circuit; and

a plurality of tethers, each tether extending between at least one of the integrated circuits and at least one of the anchors.

20. The wafer of claim 19, wherein each of the integrated circuits is encapsulated by an inorganic capping layer.

21. The wafer of claim 19, wherein the plurality of anchors are inorganic semiconductor anchors.

22. The wafer of claim 19, wherein each multi-layer electrical interconnect network comprises a plurality of interlayer dielectric layers.

23. The wafer of claim 19, wherein the plurality of tethers comprises a semiconductor active layer with a plurality of openings formed therein.

24. The wafer of claim 19, wherein a surface, opposite the substrate, of each anchor, a surface, opposite the substrate, of each tether, and a surface, opposite the substrate, of each semiconductor active layer are in a common plane.

25. The wafer of claim 19, wherein the each integrated circuit comprises one or more thin-film transistors.

26. The wafer of claim 19, comprising a patterned sacrificial layer disposed on the substrate, wherein the semiconductor active layer of each of the plurality of integrated circuits is disposed on the patterned sacrificial layer.

27. The wafer of claim 19, wherein the plurality of tethers and the semiconductor active layer of each of the integrated circuits collectively are formed of a patterned semiconductor layer.

28. The wafer of claim 27, wherein the patterned semiconductor layer comprises a plurality of openings that extend from a first surface of the patterned semiconductor layer to a second surface of the patterned semiconductor layer.

29. The wafer of claim 28, wherein the plurality of openings define the plurality of tethers.

30. A wafer of integrated circuit devices, comprising:

a substrate;

a patterned sacrificial layer on the substrate;

a patterned semiconductor active layer on the patterned sacrificial layer; and

a patterned field oxide layer on the patterned semiconductor layer,

a plurality of integrated circuits, each integrated circuit comprising a semiconductor-on-insulator substrate collectively defined by the patterned sacrificial layer, the patterned semiconductor layer, and the patterned field oxide layer collectively;

one or more anchors on the substrate;

a plurality of tethers, wherein each integrated circuit is connected to at least one of the one or more anchors by one or more tethers;

a plurality of multi-layer electrical interconnect networks, wherein one or more multi-layer electrical interconnect networks is disposed on the active semiconductor layer of each respective integrated circuit, and

a patterned capping layer at least partially on the multi-layer electrical interconnect networks, an upper surface of the semiconductor active layers, and a surface of the anchors to thereby define a plurality of suspended integrated circuits that are individually encapsulated by the patterned capping layer.

31. The wafer of claim 30, wherein the sacrificial layer is a space over which the integrated circuits are suspended by the one or more tethers.

32. The wafer of claim 30, wherein the plurality of anchors are inorganic semiconductor anchors.

33. The wafer of claim 30, wherein each multi-layer electrical interconnect network comprises a plurality of interlayer dielectric layers.

34. The wafer of claim 30, wherein the plurality of tethers comprises a semiconductor active layer with a plurality of openings formed therein.

35. The wafer of claim 30, wherein a surface, opposite the substrate, of each anchor, a surface, opposite the substrate, of each tether, and a surface, opposite the substrate, of each semiconductor active layer are in a common plane.

36. The wafer of claim 30, wherein the each integrated circuit comprises one or more thin-film transistors.

37. The wafer of claim 30, comprising a patterned sacrificial layer disposed on the substrate, wherein the semiconductor active layer of each of the plurality of integrated circuits is disposed on the patterned sacrificial layer.

38. The wafer of claim 30, wherein:

the plurality of tethers and the semiconductor active layer of each of the integrated circuits collectively are formed of a patterned semiconductor layer;

the patterned semiconductor layer comprises a plurality of openings that extend from a first surface of the patterned semiconductor layer to a second surface of the patterned semiconductor layer; and

the plurality of openings define the plurality of tethers.