HKMG HIGH VOLTAGE CMOS FOR EMBEDDED NON-VOLATILE MEMORY

• US 20160005756A1
• Filed: 07/07/2014
• Published: 01/07/2016
• Est. Priority Date: 07/07/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak-Lay, Wu, Wei Cheng, Kao, Ya-Chen, Lu, Yi Hsien
• Granted Patent: US 9,659,953 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Claims

1. An integrated circuit (IC), comprising:

an embedded memory region comprising an embedded non-volatile memory (NVM) device; and

a periphery region comprising a high voltage high-κ

metal gate (HV HKMG) transistor disposed over a high voltage (HV) gate insulating layer, and a periphery circuit disposed over a gate oxide layer.

2. The IC of claim 1, wherein the HV HKMG transistor is disposed at a location between the embedded NVM device and the periphery circuit.

3. The IC of claim 1, wherein the periphery region is separated from the embedded memory region by a boundary region.

4. The IC of claim 1, wherein the HV gate insulating layer is thicker than the gate oxide layer.

5. The IC of claim 1, wherein the periphery circuit comprises a static random access memory (SRAM) cell, an input/output cell or a core cell.

6. An integrated circuit (IC) comprising:

a semiconductor substrate including a periphery region and a memory cell region separated by a boundary region;

a pair of split gate flash memory cells disposed on the memory cell region;

a HKMG logic circuit disposed over a gate oxide layer on the periphery region; and

a high voltage (HV) high-κ

metal gate (HKMG) transistor disposed over a HV gate insulating layer on the periphery region at a position between the boundary region and the HKMG logic circuit.

7. The IC of claim 6, wherein:

the gate oxide layer has a first thickness;

the HV gate insulating layer has a second thickness; and

the second thickness is larger than the first thickness.

8. The IC of claim 7, wherein the HV HKMG transistor and the HKMG logic circuit comprise:

a high-κ

dielectric layer disposed over the HV gate insulating layer and the gate oxide layer;

an etch-stop layer disposed over the high-κ

dielectric layer; and

a metal gate layer disposed over the etch-stop layer.

9. The IC of claim 8, wherein each split gate flash memory cell comprises:

a select gate (SG);

a memory gate (MG);

a charge-trapping layer arranged between neighboring sidewalls of the MG and the SG, wherein the charge-trapping layer extends under the MG; and

sidewall spacer abutting an outer sidewall of the MG.

10. The IC of claim 9, wherein the pair of split gate flash memory cells resides over a first dielectric layer and a second dielectric layer fills the space between two neighboring cells.

11. The IC of claim 10, further comprising:

source/drain regions and isolation zones disposed within the semiconductor substrate;

a salicide layer formed over the semiconductor substrate in the source/drain regions;

a contact etch-stop layer (CESL) disposed over the salicide layer; and

metal contacts extending to active regions.

12. The IC of claim 11, wherein:

the semiconductor substrate comprises Si (silicon);

the SG and the MG comprise poly silicon or metal;

the first dielectric layer comprises SiON (silicon oxynitride), SiO2 (silicon dioxide), or SiN (silicon nitride);

the second dielectric layer comprises SiON, SiO2, or SiN;

the sidewall spacer comprises SiON, SiO2, or SiN; and

the high-κ

dielectric layer comprises HfO (hafnium oxide), HfSiO (hafnium silicon oxide), HfAlO (hafnium aluminum oxide), or HfTaO (hafnium tantalum oxide).

13. A method of forming an integrated circuit (IC) comprising:

providing a semiconductor substrate comprising a first region and a second region;

forming a non-volatile memory (NVM) device over the first region;

selectively forming a high voltage (HV) gate insulating layer over the semiconductor substrate in the second region;

forming a HV high-κ

metal gate (HKMG) transistor over the HV gate insulating layer; and

forming one or more HKMG CMOS devices in the second region.

14. The method of claim 13, wherein forming the HV gate insulating layer comprises:

forming a first oxide layer over the first and second regions;

forming a high temperature oxide (HTO) layer over the first oxide layer; and

patterning and etching the HTO layer to form the HV gate insulating layer.

15. The method of claim 14, wherein forming the HTO layer comprises rapid thermal annealing and etching the HTO layer comprises wet etching.

16. The method of claim 15, wherein:

a boundary region between the NVM device and the HV HKMG transistor in the semiconductor substrate, comprises a STI (shallow trench isolation) region;

the NVM device is formed over first region, prior to forming, patterning and etching the HTO layer; and

no wet etching occurs over the STI region in the boundary region.

17. The method of claim 13, wherein forming the one or more HKMG CMOS devices comprises:

forming a gate oxide layer over the first and second regions;

patterning and etching the gate oxide layer, to remove it from a top surface of the HV gate insulating layer;

depositing a high-κ

dielectric layer over the first and second regions;

depositing an etch stop layer over the high-κ

dielectric layer;

depositing a sacrificial gate poly layer over the etch stop layer;

forming a hard mask layer over the sacrificial gate poly layer; and

patterning and etching the hard mask layer and the layers underneath to form gate stacks.

18. The method of claim 17, further comprising:

performing a first CMP on the hard mask layer to stop at a top surface of the sacrificial gate poly layer;

removing the sacrificial poly layer to form openings in the gate stacks;

depositing a metal gate electrode layer in the openings; and

performing a second CMP on the metal gate electrode layer.

19. The method of claim 18, wherein the metal gate electrode layer comprises Ti (titanium), TiN (titanium nitride), TiAl (titanium aluminum) or TaN (tantalum nitride).

20. The method of claim 17, wherein:

thickness of the HV gate insulating layer ranges between 80 Angstroms and 200 Angstroms;

thickness of the sacrificial gate poly layer is approximately 680 Angstroms; and

thickness of the hard mask layer is approximately 1100 Angstroms.