CURRENT COUNTING ANALOG-TO-DIGITAL CONVERTER FOR LOAD CURRENT SENSING INCLUDING DYNAMICALLY BIASED COMPARATOR
First Claim
1. A circuit comprising:
- a first capacitor configured to receive a sense current in a first mode;
a second capacitor configured to receive a sense current in a second mode;
a comparator coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode and coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode;
a reset circuit to discharge the first capacitor in the second mode and to discharge the second capacitor in the first mode in response to the count signal; and
a counter incrementing a count of a number of occurrences of the count signal.
1 Assignment
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Accused Products
Abstract
In one embodiment, a circuit comprises first and second capacitors configured to receive a sense current in first and second modes, respectively. A comparator is coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode. The comparator is coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode. A reset circuit discharges the first capacitor in the second mode and the second capacitor in the first mode in response to the count signal. A counter increments a count of a number of occurrences of the count signal.
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Citations
15 Claims
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1. A circuit comprising:
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a first capacitor configured to receive a sense current in a first mode; a second capacitor configured to receive a sense current in a second mode; a comparator coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode and coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode; a reset circuit to discharge the first capacitor in the second mode and to discharge the second capacitor in the first mode in response to the count signal; and a counter incrementing a count of a number of occurrences of the count signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit comprising:
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first means for integrating charge received from a current source in a first mode; second means for integrating charge received from the current source in a second mode; means for comparing a voltage of the first means for integrating charge to a reference voltage and generating a count signal in response to the voltage of the first means for integrating charge reaching the reference voltage in the first mode and for comparing a voltage of the second means for integrating charge to the reference voltage and generating the count signal in response to the voltage of the second means for integrating charge reaching the reference voltage in the second mode; means for counting a number of occurrences of the count signal; first means for discharging the first means for integrating charge in response to the count signal in the second mode; and second means for discharging the second means for integrating charge in response to the count signal in the first mode. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method comprising:
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storing charge received from a current source in a first capacitor in a first mode; storing charge received from a current source in a second capacitor in a second mode; discharging the first capacitor in the second mode; discharging the second capacitor in the first mode; comparing a voltage of the first capacitor to a reference voltage and generating a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode; comparing a voltage of the second capacitor to the reference voltage and generating the count signal in response to the voltage of the second reaching the reference voltage in the second mode; counting a number of occurrences of the count signal; and switching between the first and second modes in response to the count signal.
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Specification