METHOD OF ATTACHING A LIGHT EMITTING DEVICE TO A SUPPORT SUBSTRATE

• US 20160020198A1
• Filed: 09/29/2015
• Published: 01/21/2016
• Est. Priority Date: 06/01/2011
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Koninklijke Philips N.V.
• Inventors: STEIGERWALD, DANIEL ALEXANDER, BHAT, JEROME CHANDRA, AKRAM, SALMAN
• Granted Patent: US 9,431,581 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 25/075 the devices being of a type provided for in group H01L33/00
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/483 Containers
• CPC Class Codes: H01L 33/50 Wavelength conversion elements
• CPC Class Codes: H01L 33/58 Optical field-shaping elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A method according to embodiments of the invention includes providing a wafer of semiconductor light emitting devices, each semiconductor light emitting device including a light emitting layer sandwiched between an n-type region and a p-type region. A wafer of support substrates is provided, each support substrate including a body. The wafer of semiconductor light emitting devices is bonded to the wafer of support substrates. Vias are formed extending through the entire thickness of the body of each support substrate.

Claims

1. A method comprising:

bonding a wafer of semiconductor light emitting devices, each semiconductor light emitting device comprising a light emitting layer sandwiched between an n-type region and a p-type region, to a wafer of support substrates, each support substrate comprising a body; and

after bonding the wafer of semiconductor light emitting devices to the wafer of support substrates, forming vias extending through the entire thickness of the body of each support substrate;

wherein said bonding comprises bonding at a temperature less than 300°

C.

2. The method of claim 1 wherein said bonding comprises bonding at a temperature between 230°

C. and 275°

C.

3. The method of claim 1 wherein said bonding comprises bonding at a temperature less than 150°

C.

4. The method of claim 1 wherein said bonding comprises bonding at a temperature between 100°

C. and 250°

C.

5. The method of claim 1 further comprising thinning the body of each support substrate prior to said forming vias.

6. The method of claim 1 wherein bonding the wafer of semiconductor light emitting devices to the wafer of support substrates comprises bonding via at least one bonding layer.

7. The method of claim 6 wherein the at least one bonding layer comprises regions of metal separated by regions of dielectric, wherein the regions of metal and regions of dielectric are formed on a top surface of the body of each support substrate.

8. The method of claim 6 wherein the at least one bonding layer comprises a polymer layer formed on the wafer of semiconductor light emitting devices.

9. The method of claim 6 wherein the at least one bonding layer comprises an organic adhesive formed on the wafer of semiconductor light emitting devices.

10. The method of claim 6 wherein the at least one bonding layer comprises a first dielectric bonding layer formed on the wafer of semiconductor light emitting devices and a second dielectric bonding layer formed on the wafer of support substrates.

11. The method of claim 1 further comprising dicing the wafer of semiconductor light emitting devices into individual light emitting device chips after bonding the wafer of semiconductor light emitting devices to the wafer of support substrates.

12. A device comprising:

a semiconductor light emitting device comprising;

a light emitting layer sandwiched between an n-type region and a p-type region;

an n-contact disposed on the n-type region, wherein the n-contact is set back from an edge of the n-type region; and

a reflective dielectric layer disposed on said edge of the n-type region;

a support substrate comprising a body, wherein a width of the support substrate is the same as a width of the semiconductor light emitting device; and

a plurality of vias formed in the body.

13. The device of claim 12 further comprising a polymer layer disposed over the reflective dielectric layer.

14. The device of claim 13 wherein the polymer layer is doped with a light absorbing material.

15. A method comprising:

in a first aligning procedure, aligning a wafer of semiconductor light emitting devices, each semiconductor light emitting device comprising a light emitting layer sandwiched between an n-type region and a p-type region, with a wafer of support substrates, each support substrate comprising a body;

bonding the wafer of semiconductor light emitting devices to the wafer of support substrates;

in a second aligning procedure, aligning an etch mask with metallizations formed on the wafer of semiconductor light emitting devices; and

after bonding the wafer of semiconductor light emitting devices to the wafer of support substrates, forming vias extending through an entire thickness of the body of each support substrate, wherein the vias are defined by the etch mask;

wherein the first aligning procedure is less precise than the second aligning procedure.

16. The method of claim 15 wherein the first aligning procedure comprises visual alignment.

17. The method of claim 15 wherein the second aligning procedure comprises one of IR alignment and backside alignment.

18. The method of claim 15 wherein at the time of bonding, the wafer of support substrates contains no features.

19. The method of claim 15 wherein said bonding comprises bonding via a bonding layer.

20. The method of claim 15 wherein said bonding comprises bonding at a temperature between 100°

C. and 250°

C.