SEMICONDUCTOR DEVICE

• US 20160027732A1
• Filed: 01/29/2014
• Published: 01/28/2016
• Est. Priority Date: 01/29/2014
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Igarashi, Takayuki, Funaya, Takuo
• Granted Patent: US 9,711,451 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]

Abstract

Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

Claims

1. A semiconductor device comprising:

a substrate;

a first insulating film formed on an upper portion of the substrate;

a first coil and a first wiring formed on the first insulating film;

a second insulating film formed on the first coil and the first wiring;

a second wiring formed on the second insulating film;

a third insulating film formed on the second wiring; and

a second coil and a third wiring formed on the third insulating film,

wherein a distance between the second coil and the third wiring is longer than a distance between the second coil and the second wiring.

2. The semiconductor device according to claim 1,

wherein the distance between the second coil and the second wiring is set to be longer than a sum of film thicknesses of the second insulating film and the third insulating film that are positioned between the first coil and the second coil.

3. The semiconductor device according to claim 2,

wherein each of the second wiring, the second coil and the third wiring is a film containing aluminum.

4. The semiconductor device according to claim 3,

wherein each of the second wiring, the second coil and the third wiring has a film thickness of 3 μ

m or more.

5. The semiconductor device according to claim 4,

wherein each of the second insulating film and the third insulating film is formed of an inorganic insulating film.

6. The semiconductor device according to claim 5,

wherein a sum of film thicknesses of the second insulating film and the third insulating film that are positioned between the first coil and the second coil is 5 μ

m or more.

7. The semiconductor device according to claim 1,

wherein the third insulating film includes a first film formed between the second wirings and a second film formed on the first film.

8. The semiconductor device according to claim 1,

wherein the second coil includes a first pad and a coil portion surrounding the first pad, and the first pad has a planar shape formed into a polygonal shape having more sides than those of a square shape.

9. The semiconductor device according to claim 1,

wherein the second wiring and the third wiring are connected to each other in an opening formed in the third insulating film, and the opening has a planar shape formed into a polygonal shape having more sides than those of a square shape.

10. A semiconductor device comprising:

a substrate;

a first insulating film formed on an upper portion of the substrate;

a first coil and a first wiring formed on the first insulating film;

a second insulating film formed on the first coil and the first wiring;

a second wiring and a first dummy wiring formed on the second insulating film;

a third insulating film formed on the second wiring and the first dummy wiring; and

a second coil and a third wiring formed on the third insulating film,

wherein the third insulating film has a first film formed between the second insulating film and the first dummy wiring and a second film formed on the first film.

11. The semiconductor device according to claim 10,

wherein a distance between the second coil and the third wiring is set to be longer than a distance between the second coil and the second wiring.

12. The semiconductor device according to claim 11,

wherein the distance between the second coil and the second wiring is set to be longer than a sum of film thicknesses of the second insulating film and the third insulating film that are positioned between the first coil and the second coil.

13. The semiconductor device according to claim 12,

wherein each of the second wiring, the second coil, the third wiring and the first dummy wiring is a film containing aluminum.

14. The semiconductor device according to claim 13,

wherein each the second insulating film and the third insulating film is formed of an inorganic insulating film.

16. The semiconductor device according to claim 14, further comprising:

a second groove which is formed along an outer periphery of the second region, and penetrates the semiconductor to reach the fourth insulating film; and

a fifth insulating film formed inside the second groove.

15. A semiconductor device comprising:

a substrate having a first region and a second region and including a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer;

a first insulating film formed on an upper portion of the substrate;

a first coil and a first wiring formed on the first insulating film;

a second insulating film formed on the first coil and the first wiring;

a second wiring formed on the second insulating film;

a third insulating film formed on the second wiring; and

a second coil and a third wiring formed on the third insulating film,

wherein the first coil and the second coil are formed in the first region, and the second wiring and an active element connected to the second wiring are formed in the second region,

the semiconductor device further comprising;

a first groove which is formed along an outer periphery of the first region, and penetrates the semiconductor to reach the insulating layer; and

a fourth insulating film formed inside the first groove.

17. The semiconductor device according to claim 15,

wherein a distance between the second coil and the third wiring is set to be longer than a distance between the second coil and the second wiring.

18. The semiconductor device according to claim 17,

wherein the distance between the second coil and the second wiring is set to be longer than a sum of film thicknesses of the second insulating film and the third insulating film that are positioned between the first coil and the second coil.

19. The semiconductor device according to claim 18,

wherein each of the second wiring, the second coil and the third wiring is a film containing aluminum.

20. The semiconductor device according to claim 19,

wherein each of the second insulating film and the third insulating film is formed of an inorganic insulating film.