SEMICONDUCTOR DEVICE

• US 20160027918A1
• Filed: 06/17/2015
• Published: 01/28/2016
• Est. Priority Date: 07/22/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Byeong Chan Lee, Dong Chan Suh, Kwan Heum Lee, Nam Kyu Kim, Su Jin Jung
• Inventors: LEE, Kwan Heum, KIM, Gyeom, KIM, Nam Kyu, SUH, Dong Chan, LEE, Byeong Chan, LEE, Cho Eun, JUNG, Su Jin, YOON, Ji Eon
• Granted Patent: US 9,761,719 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a device isolating layer embedded within the semiconductor substrate and defining an active region;

a channel region formed in the active region;

a gate electrode disposed above the channel region;

a gate insulating layer provided between the channel region and the gate electrode; and

a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

2. The semiconductor device of claim 1, wherein the silicon germanium epitaxial layer further includes a buffer epitaxial layer having a germanium concentration lower than the first concentration, below the first epitaxial layer.

3. The semiconductor device of claim 2, wherein the germanium concentration of the buffer epitaxial layer is in a range of 10 at % to 25 at %.

4. The semiconductor device of claim 1, wherein the first concentration is in a range of 25 at % to 50 at %, the second concentration is in a range of 50 at % to 90 at %, and the third concentration is in a range of 25 at % to 50 at %.

5. The semiconductor device of claim 1, further comprising:

a contact plug disposed on the silicon germanium epitaxial layer,

wherein the contact plug extends into the third epitaxial layer.

6. The semiconductor device of claim 5, further comprising:

a metal silicide layer disposed between the silicon germanium epitaxial layer and the contact plug,

wherein the metal silicide layer is positioned in an upper portion of the second epitaxial layer.

8. The semiconductor device of claim 1, further comprising a silicon capping layer and an etch stopping layer,

wherein the silicon capping layer and etch stopping layer are sequentially disposed on the silicon germanium epitaxial layer.

9. The semiconductor device of claim 1, wherein the active region includes a recessed region in a location corresponding to both sides of the gate electrode, and the silicon germanium epitaxial layer is formed in the recessed region of the active region.

10. The semiconductor device of claim 1, wherein the active region includes a plurality of active layers, and the device isolating layer is provided to fill a space between the plurality of active layers to a predetermined height,

a width of the active region is reduced in an upward direction and an upper portion of the active region protrudes upwardly above the device isolating layer.

12. The semiconductor device of claim 1, wherein the gate insulating layer includes at least one high-k dielectric layer and the gate electrode is at least comprised of one of metal silicide and a metal.

16. The semiconductor device of claim 8, further comprising:

a contact plug disposed on the silicon germanium epitaxial layer,

wherein the contact plug extends into the silicon capping layer; and

a metal silicide layer disposed between the bottom surface of the third epitaxial layer and the contact plug.

7. (canceled)

11. (canceled)

13-15. -15. (canceled)

17-20. -20. (canceled)

21. A semiconductor device comprising:

a semiconductor substrate;

a device isolating layer on the semiconductor substrate defining an active region;

a channel region formed in the active region;

a gate electrode disposed above the channel region;

a gate insulating layer provided between the channel region and the gate electrode; and

a silicon germanium epitaxial source/drain region adjacent to the channel region including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer on the first epitaxial layer containing a second concentration of germanium higher than the first concentration, and a third epitaxial layer on the second epitaxial layer containing a third concentration of germanium lower than the second concentration.

22. The semiconductor device of claim 21, wherein the silicon germanium epitaxial source/drain region further includes a buffer epitaxial layer located in a region directly below the first epitaxial layer and having a germanium concentration lower than the first concentration.

23. The semiconductor device of claim 21, wherein the second concentration is between one and four times greater than the each of the first and third concentrations, and

wherein the first and third concentrations are different.

24. The semiconductor device of claim 22,

wherein the first concentration is between one and five times greater than the germanium concentration of the buffer epitaxial layer, and

wherein the second concentration is between one and four times greater than each of the first and third concentrations and between two and ten times greater than the germanium concentration of the buffer epitaxial layer.

25. The semiconductor device of claim 21, further comprising:

a contact plug disposed on the silicon germanium epitaxial source/drain region,

wherein the contact plug extends into the third epitaxial layer.

26. The semiconductor device of claim 25, further comprising:

a metal silicide layer disposed between the silicon germanium epitaxial source/drain region and the contact plug,

wherein the metal silicide layer contacts the second epitaxial layer.

27. The semiconductor device of claim 25, wherein a bottom portion of the contact plug has a serrated shape corresponding to an upper portion of the silicon germanium epitaxial layers.

28. The semiconductor device of claim 21, wherein the silicon germanium epitaxial source/drain region is doped with a p-type impurity and a concentration of the p-type impurity is varied in correlation to the concentration of germanium.

31. The semiconductor device of claim 21, wherein the silicon germanium epitaxial layer further comprises:

a first interfacial layer disposed between the buffer epitaxial layer and the first epitaxial layer;

a second interfacial layer disposed between the first epitaxial layer and the second epitaxial layer; and

a third interfacial layer disposed between the second epitaxial layer and the third epitaxial layer.

29-30. -30. (canceled)

32-33. -33. (canceled)