MULTI-LANE N-FACTORIAL (N!) AND OTHER MULTI-WIRE COMMUNICATION SYSTEMS

• US 20160028534A1
• Filed: 10/05/2015
• Published: 01/28/2016
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sengoku, Shoichiro
• Granted Patent: US 9,735,948 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0276 Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.

Claims

1. A receiving device, comprising:

a processing circuit configured to;

receive a sequence of symbols over a multi-wire link,

receive a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link, and

decode the sequence of symbols using the clock signal.

2. The receiving device of claim 1, wherein:

a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols, and

the processing circuit is configured to decode the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.

3. The receiving device of claim 1, wherein the processing circuit configured to decode is further configured to convert the sequence of symbols to a set of data bits using the clock signal.

4. The receiving device of claim 3, wherein the processing circuit configured to convert the sequence of symbols to the set of data bits is further configured to:

use a transcoder to convert the sequence of symbols to a set of transition numbers; and

convert the set of transition numbers to the set of data bits.

5. The receiving device of claim 1, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, where N is an integer greater than 1.

6. The receiving device of claim 1, wherein at least one line of the multi-wire link bi-directional.

7. The receiving device of claim 6, the processing circuit further configured to transmit a second sequence of symbols over the at least one bi-directional line based on the clock signal received via the dedicated clock line.

8. The receiving device of claim 7, wherein the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link.

9. A method of data communications at a receiving device, comprising:

receiving a sequence of symbols over a multi-wire link;

receiving a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link; and

decoding the sequence of symbols using the clock signal.

10. The method of claim 9, wherein:

a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols, and

the sequence of symbols are decoded using the clock signal received via the dedicated clock line while ignoring the second clock signal.

11. The method of claim 9, wherein the decoding includes converting the sequence of symbols to a set of data bits using the clock signal.

12. The method of claim 11, wherein the converting the sequence of symbols to the set of data bits includes:

using a transcoder to convert the sequence of symbols to a set of transition numbers; and

converting the set of transition numbers to the set of data bits.

13. The method of claim 9, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, where N is an integer greater than 1.

14. The method of claim 9, wherein at least one line of the multi-Eire link is bi-directional.

15. The method of claim 14, further including transmitting a second sequence of symbols over the at least one bi-directional line based on the clock signal received via the dedicated clock line.

16. The method of claim 15, wherein the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link.

17. A transmitting device, comprising:

a processing circuit configured to;

encode data bits into a sequence of symbols,

transmit the sequence of symbols over a multi-wire link, and

transmit a clock signal associated with the sequence of symbols via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link.

18. The transmitting device of claim 17, the processing circuit further configured to embed a second clock signal in the sequence of symbols, wherein the second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols.

19. The transmitting device of claim 17, wherein the processing circuit configured to encode the data bits is further configured to:

use a transcoder to convert the data hits to a set of transition numbers; and

convert the set of transition numbers to obtain the sequence of symbols.

20. The transmitting device of claim 17, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, where N is an integer greater than 1.

21. The transmitting device of claim 17, wherein at least one line of the multi-wire link is hi-directional.

22. The transmitting device of claim 21, the processing circuit further configured to receive a second sequence of symbols over the at least one bi-directional line based on the clock signal transmitted via the dedicated clock line.

23. The transmitting device of claim 22, wherein the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link.

24. A method of data communications at a transmitting device, comprising:

encoding data bits into a sequence of symbols;

transmitting the sequence of symbols over a multi-wire link; and

transmitting a clock signal associated with the sequence of symbols via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link.

25. The method of claim 24, further comprising embedding a second clock signal in the sequence of symbols, wherein the second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols.

26. The method of claim 24, wherein the encoding the data bits includes:

using a transcoder to convert the data bits to a set of transition numbers; and

converting the set of transition numbers to obtain the sequence of symbols.

27. The method of claim 24, wherein each symbol in the sequence of symbols corresponds to a signaling state of N wires of the multi-wire link, where N is an integer greater than 1.

28. The method of claim 24, wherein at least one line of the multi-wire link is bi-directional.

29. The method of claim 28, further including receiving a second sequence of symbols over the at least one bi-directional line based on the clock signal transmitted via the dedicated clock line.

30. The method of claim 29, wherein the dedicated clock line is bi-directional and can be driven from any device transmitting over the multi-wire link.