Semiconductor Devices and Methods of Fabricating the Same

• US 20160035676A1
• Filed: 04/08/2015
• Published: 02/04/2016
• Est. Priority Date: 07/29/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Im, Dong-Hyun, Park, Hyun, Kim, Sangwon, Park, Seongjun, Shin, Hyeon Jin, Lim, Hanjin, Lee, Soongun, Lee, Chang Seok
• Granted Patent: US 9,337,149 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/033 : the capacitor extending over the transistor
• CPC Class Codes: H10B 12/0335 : Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/05 : Making the transistor
• CPC Class Codes: H10B 12/315 : with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/482 : Bit lines
• CPC Class Codes: H10B 12/485 : Bit line contacts

Abstract

Semiconductor devices may include a substrate including an active region defined by a device isolation layer, source/drain regions in the active region, word lines extending in a first direction parallel to the active region and being arranged in a second direction crossing the first direction, a bit line pattern extending in the second direction and crossing over a portion of the active region positioned between the word lines, and a graphene pattern covering at least a portion of the bit line pattern.

Claims

1. A semiconductor device, comprising:

a substrate comprising an active region defined by a device isolation layer;

source/drain regions in the active region;

word lines that extend in a first direction parallel to the active region and that are arranged in a second direction crossing the first direction;

a bit line pattern that extends in the second direction and that crosses over a portion of the active region positioned between the word lines; and

a graphene pattern that covers at least a portion of the bit line pattern.

2. The device of claim 1, wherein the bit line pattern comprises a first bit line pattern, a second bit line pattern, and a third bit line pattern that are sequentially stacked on the substrate, and

wherein the graphene pattern is on a sidewall of the third bit line pattern.

3. The device of claim 1, wherein the bit line pattern comprises a first bit line pattern, a second bit line pattern, a third bit line pattern, that are sequentially stacked on the substrate, and a seed pattern on a sidewall of the third bit line pattern, and

wherein the graphene pattern is on the seed pattern.

4. The device of claim 3, wherein the first and second bit line patterns have substantially a same width, and

wherein a sum of widths of the third bit line pattern and the seed pattern is substantially equal to a width of one of the first or second bit line patterns.

5. The device of claim 1, wherein the graphene pattern is on a top surface of the bit line pattern.

6. The device of claim 5, wherein the graphene pattern comprises a first graphene pattern and a second graphene pattern that are sequentially stacked on the top surface of the bit line pattern, and

wherein the first graphene pattern has a first crystal structure and the second graphene pattern has a second crystal structure that is different from the first crystal structure.

7. The device of claim 6, wherein the first and second graphene patterns comprise a plurality of stacked graphene films,

wherein the graphene films of the first graphene pattern cover the top surface of the bit line pattern in a substantially discontinuous and parallel manner, and

wherein the graphene films of the second graphene pattern cover the top surface of the bit line pattern in a substantially continuous and parallel manner.

8. The device of claim 1, further comprising,

an interlayered insulating layer on the substrate that covers the bit line pattern and the graphene pattern;

a storage node contact that penetrates the interlayered insulating layer and that is in contact with one of the source/drain regions; and

a capacitor on the storage node contact.

9. The device of claim 8, wherein the capacitor comprises a lower electrode, a dielectric layer that covers the lower electrode, and an upper electrode that covers the dielectric layer,

wherein the lower electrode comprises a first lower electrode and a second lower electrode that covers the first lower electrode, and

wherein the second lower electrode comprises graphene.

10. The device of claim 2, wherein the first bit line pattern comprises polysilicon or doped polysilicon.

11. The device of claim 2, wherein the second bit line pattern comprises TiN, Ti/TiN, TiSiN, TaN, and/or WN.

12. The device of claim 2, wherein the third bit line pattern comprises tungsten, aluminum, copper, nickel, and/or cobalt.

13. A method of fabricating a semiconductor device, comprising:

forming an electrode layer on a substrate;

forming a graphene layer on the electrode layer;

forming a mask pattern on the graphene layer, and

etching the graphene layer and the electrode layer using the mask pattern as an etch mask to form an electrode pattern,

wherein the forming of the graphene layer comprises;

supplying a hydrogen gas on the electrode layer that couples hydrogen atoms onto a surface of the electrode layer;

supplying a carbon-containing reaction gas on the electrode layer that replaces the hydrogen atoms with carbon atoms; and

growing the graphene layer from the carbon atoms.

14. The method of claim 13, wherein the electrode layer comprises a TiN layer, a Ti/TiN layer, a TiSiN layer, a TaN layer, a WN layer, a tungsten layer, an aluminum layer, a copper layer, a nickel layer, a cobalt layer, a poly-silicon layer, or a doped poly-silicon layer.

15. The method of claim 13, before the forming of the electrode layer, further comprising:

forming a device isolation layer that defines an active region in the substrate;

forming source/drain regions in the active region;

forming bit lines that cross the active region; and

forming a bit line node contact that connects a corresponding one of the bit lines to the active region.

16. A semiconductor device, comprising:

a substrate comprising an active region defined by a device isolation layer;

a bit line that crosses over a portion of the active region and that comprises;

a plurality of bit line patterns that are sequentially stacked on the substrate, wherein at least one bit line pattern of the plurality of bit line patterns comprises a different material than another one of the plurality of bit line patterns; and

a graphene pattern that is on one of the plurality of bit line patterns; and

an interlayered insulating layer that is on the substrate, on the plurality of bit line patterns, and on the graphene pattern.

17. The semiconductor device of claim 16, wherein the graphene pattern comprises a plurality of stacked graphene films.

18. The semiconductor device of claim 17, wherein a bit line pattern of the plurality of bit line patterns has a surface covered by the graphene pattern.

19. The semiconductor device of claim 18, further comprising:

a seed pattern that is between the graphene pattern and the surface of the bit line pattern of the plurality of bit line patterns covered by the graphene pattern, and

wherein the bit line pattern of the plurality of bit line patterns with the surface covered by the graphene pattern has a smaller width than another one of the plurality of bit line patterns.

20. The semiconductor device of claim 18, wherein the graphene pattern comprises a first graphene pattern and a second graphene pattern that are sequentially stacked parallel to a top surface of the plurality of bit line patterns, and

wherein the first graphene pattern has a first crystal structure and the second graphene pattern has a second crystal structure that is different from the first crystal structure.