BUFFER LAYER(S) ON A STACKED STRUCTURE HAVING A VIA
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Abstract
A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.
40 Citations
34 Claims
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1-14. -14. (canceled)
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15. A method comprising:
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bonding a first substrate to a second substrate, the second substrate comprising a semiconductor substrate; forming a via from a side of the semiconductor substrate and at least extending through the semiconductor substrate; forming a first stress buffer layer on the side of the semiconductor substrate; forming a post-passivation interconnect (PPI) structure on the first stress buffer layer and electrically coupled to the via; and forming a second stress buffer layer on the PPI structure and the first stress buffer layer. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A method comprising:
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bonding a first substrate to a second substrate, the first substrate comprising a semiconductor substrate and an interconnect structure, the interconnect structure being on a first side of the semiconductor substrate, the interconnect structure being disposed between the semiconductor substrate and the second substrate after the bonding; forming a conductive pad on a second side of the semiconductor substrate opposite from the first side of the semiconductor substrate, the conductive pad being electrically coupled to the interconnect structure; forming a passivation layer on the conductive pad and on the second side of the semiconductor substrate; forming a first stress buffer layer on the passivation layer; forming an interconnect structure on the first stress buffer layer and through an opening through the first stress buffer layer and the passivation layer to the conductive pad; and forming a second stress buffer layer on the interconnect structure and the first stress buffer layer. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A method comprising:
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bonding a first substrate to a second substrate, the first substrate comprising a first semiconductor substrate and a first interconnect structure on the first semiconductor substrate, the second substrate comprising a second semiconductor substrate and a second interconnect structure on the second semiconductor substrate, wherein after the bonding, the first interconnect structure and the second interconnect structure are disposed between the first semiconductor substrate and the second semiconductor substrate; forming a through via extending from a side of the first semiconductor substrate opposite from the first interconnect structure through the first semiconductor substrate at least to the first interconnect structure; forming a pad on the side of the first semiconductor substrate opposite from the first interconnect structure, the pad being electrically coupled to the through via; forming a passivation layer on the pad and the first semiconductor substrate opposite from the first interconnect structure; forming a first stress buffer layer on the passivation layer, the passivation layer being disposed between the first stress buffer layer and the first semiconductor substrate; forming a post-passivation interconnect (PPI) structure on the first stress buffer layer, the PPI structure extending through an opening through the first stress buffer layer and the passivation layer to be electrically coupled to the pad; forming a second stress buffer layer on the PPI structure and the first stress buffer layer, the PPI structure being disposed at least in part between the first stress buffer layer and the second stress buffer layer; and forming an external electrical connection structure through an opening of the second stress buffer layer and contacting the PPI structure. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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Specification