SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20160049564A1
• Filed: 03/12/2015
• Published: 02/18/2016
• Est. Priority Date: 08/13/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHU, Kunmo, MOON, Changyoul, LEE, Sunghee, HWANG, Junsik
• Granted Patent: US 10,249,604 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/29082 Two-layer arrangements
• CPC Class Codes: H01L 2224/29083 Three-layer arrangements
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/29155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73217 Layer and HDI connectors
• CPC Class Codes: H01L 2224/73227 Wire and HDI connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/82101 : by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83193 : wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83204 : with a graded temperature profile
• CPC Class Codes: H01L 2224/8381 : involving forming an intermetallic compound at the bonding interface
• CPC Class Codes: H01L 2224/83825 : Solid-liquid interdiffusion
• CPC Class Codes: H01L 2224/83948 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92144 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate

Abstract

A semiconductor device includes a base substrate and a semiconductor chip on the base substrate, the semiconductor chip including a first layer structure and a second layer structure opposite to the first layer structure, at least one of the first and second layer structures including a semiconductor device portion, and a bonding structure between the first layer structure and the second layer structure, the bonding structure including a silver-tin (Ag—Sn) compound and a nickel-tin (Ni—Sn) compound.

Claims

1. A semiconductor device comprising:

a base substrate; and

a semiconductor chip on the base substrate, the semiconductor chip including,

a first layer structure and a second layer structure opposite to the first layer structure, at least one of the first and second layer structures including a semiconductor device portion, and

a bonding structure between the first layer structure and the second layer structure, the bonding structure including a silver-tin (Ag—

Sn) compound and a nickel-tin (Ni—

Sn) compound.

2. The semiconductor device of claim 1, wherein the bonding structure further includes pure Ni.

3. The semiconductor device of claim 1, wherein

the Ag—

Sn compound includes Ag₃Sn, and

the Ni—

Sn compound includes Ni₃Sn₄.

4. The semiconductor device of claim 3, wherein the bonding structure includes

an intermediate layer including the Ag₃Sn and the Ni₃Sn₄,

a first Ni layer between the intermediate layer and the first layer structure, and

a second Ni layer between the intermediate layer and the second layer structure.

5. The semiconductor device of claim 3, wherein the Ni—

Sn compound further includes Ni₃Sn.

6. The semiconductor device of claim 1, wherein the Ag content in the bonding structure is about 0.5 wt % to about 23.1 wt %.

7. The semiconductor device of claim 1, wherein the semiconductor device portion includes a light-emitting device portion.

8. The semiconductor device of claim 7, wherein

the first layer structure includes a silicon (Si) substrate,

the second layer structure includes the light-emitting device portion, and

the light-emitting device portion includes a Group III-V semiconductor.

9. The semiconductor device of claim 1, wherein

the first layer structure includes a first substrate and a first semiconductor device portion on the first substrate, and

the second layer structure includes a second substrate and a second semiconductor device portion on the second substrate.

10. The semiconductor device of claim 1, wherein at least one third layer structure is bonded onto the second layer structure.

11. The semiconductor device of claim 1, wherein a die shear strength of the bonding structure is 32 MPa or more.

12. The semiconductor device of claim 1, wherein a re-melting temperature of the bonding structure is 350°

C. or more.

13. The semiconductor device of claim 1, wherein an average elastic modulus of an intermetallic compound in the bonding structure is 124 GPa to 152 GPa.

14. The semiconductor device of claim 1, wherein an average hardness of an intermetallic compound in the bonding structure is 4.5 GPa to 9 GPa.

15. A method of manufacturing a semiconductor device, the method comprising:

forming a first metal layer on a first substrate structure, the first metal layer including a first nickel (Ni) layer and a first tin (Sn) layer;

forming a second metal layer on a second substrate structure, the second metal layer including a second Ni layer;

forming a capping layer between the first and second metal layers, the capping layer including silver (Ag); and

forming a bonding structure including,

bonding the first substrate structure of the first metal layer to the second substrate structure of the second metal layer, and

forming an intermediate layer between the first metal layer and the second metal layer by a reaction between the first and second metal layers and the capping layer, the intermediate layer including an intermetallic compound.

16. The method of claim 15, wherein the forming a second metal layer forms a second Sn layer on the second Ni layer.

17. The method of claim 15, wherein the forming a capping layer includes

forming a first Ag layer on the first metal layer, and

forming a second Ag layer on the second metal layer.

18. The method of claim 17, wherein

the forming a first Ag layer forms the first Ag layer to contact the first Sn layer, and

the forming a second Ag layer forms the second Ag layer to contact the second Ni layer.

19. The method of claim 17, wherein the forming a second metal layer forms a second Sn layer contacting the second Ag layer.

20. The method of claim 15, wherein the forming a bonding structure forms Ag₃Sn, Ni₃Sn₄, and Ni.

21. The method of claim 20, wherein the forming a bonding structure includes

forming the intermediate layer including Ag₃Sn and the Ni₃Sn₄,

forming a first residual Ni layer between the intermediate layer and the first substrate structure, and

forming a second residual Ni layer between the intermediate layer and the second substrate structure.

22. The method of claim 20, wherein the forming a bonding structure further includes forming Ni₃Sn.

23. The method of claim 15, wherein the forming a bonding structure forms the bonding structure at a temperature of 300°

C. or less.

24. The method of claim 15, wherein the forming a bonding structure forms the bonding structure using a pressure of 0.5 MPa or less.

25. The method of claim 15, further comprising:

forming a semiconductor device portion in at least one of the first and second substrate structures.

26. The method of claim 25, wherein the forming a semiconductor device portion forms at least one light-emitting device portion.

27. The method of claim 15, wherein

one of the forming a first metal layer and the forming a second metal layer forms one of the first metal layer and the second metal layer on a silicon (Si) substrate, and

the other of the forming a first metal layer and the forming a second metal layer forms one of the first metal layer and the second metal layer on one selected from a GaN substrate, a SiC substrate, a GaAs substrate, and a sapphire substrate.

28. The method of claim 15, wherein the forming a first metal layer and the forming a second metal layer forms the first metal layer and the second metal layer on a wafer-level substrate.

29. The method of claim 15, further comprising:

forming a plurality of semiconductor chips by dividing a stacked structure based on chip units, the stacked structure including the first and second substrate structures and the bonding structure therebetween; and

mounting at least one of the plurality of semiconductor chips on a base substrate.

30. The method of claim 15, further comprising:

modifying a stacked structure by removing at least a portion of the first substrate structure, the stacked structure including the first and second substrate structures and the bonding structure therebetween;

forming a plurality of semiconductor chips by dividing the modified stacked structure based on chip units; and

mounting at least one of the plurality of semiconductor chips on a base substrate.

31. A semiconductor chip comprising a bonding layer between a first layer structure and a second layer structure, the bonding layer including a silver-tin (Ag—

Sn) compound and a nickel-tin (Ni—

Sn) compound.

32. The semiconductor chip of claim 31, wherein

the Ag—

Sn compound includes Ag₃Sn, and

the Ni—

Sn compound includes Ni₃Sn₄.

33. The semiconductor chip of claim 32, wherein the bonding layer includes

an intermediate layer including the Ag₃Sn and the Ni₃Sn₄,

a first layer between the intermediate layer and the first layer, the first layer including pure Ni, and

a second layer between the intermediate layer and the second layer, the second layer including pure Ni.

34. The semiconductor chip of claim 32, wherein the Ni—

Sn compound further includes Ni₃Sn.

35. The semiconductor chip of claim 31, wherein the Ag content in the bonding layer is about 0.5 wt % to about 23.1 wt %.