METHOD OF IMPROVING ERROR CHECKING AND CORRECTION PERFORMANCE OF MEMORY

• US 20160062860A1
• Filed: 08/28/2015
• Published: 03/03/2016
• Est. Priority Date: 08/28/2014
• Status: Active Grant

• Current Assignee: SungKyunKwan University's Research & Business Foundation (SungKyunKwan University)
• Original Assignee: SungKyunKwan University's Research & Business Foundation (SungKyunKwan University)
• Inventors: YANG, Joon-Sung, HAN, Hyunseung
• Granted Patent: US 9,779,838 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A method of improving an error checking and correction performance of a memory includes replacing a defective column including a defective memory cell of the memory cell array with a spare column of a the spare cell array, wherein the memory cell array includes memory cells in a matrix and the spare cell array includes spare memory cells in a matrix to be replaced for defective memory cells; storing check bits of error correction code in at least one memory cell of the defective column; storing defect information regarding a defect of the defective memory cell; determining whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and performing error checking and correction on the memory using a memory cell selected based on a result of determining whether the at least one memory cell storing the check bits is to be used.

Claims

1. A method of improving an error checking and correction performance of a memory, the method comprising:

replacing a defective column including a defective memory cell of a memory cell array with a spare column of a spare cell array, wherein the memory cell array comprises memory cells in a matrix, and the spare cell array comprises spare memory cells in a matrix to be replaced for defective memory cells;

storing check bits of error correction code in at least one memory cell of at least one of a spare column that is not used to replace the defective column and the defective column;

storing defect information regarding the defective memory cell;

selecting whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and

performing error checking and correction on the memory using a memory cell selected based on a result of selecting whether the at least one memory cell storing the check bits is to be used.

2. The method of claim 1, wherein the storing of the defect information comprises storing the defect information in an information storing spare column which is not used to replace the defective column among spare columns of the spare cell array.

3. The method of claim 2, wherein the defect information is information regarding a location of the defective memory cell in the defective column.

4. The method of claim 3, wherein the storing of the defect information in the information storing spare column comprises storing ‘

1’

in a spare memory cell of the information storing spare column arranged in a row in which the defective memory cell is present when the defective memory cell is present, and storing ‘

0’

in a spare memory cell of the information storing spare column arranged in a row in which the defective memory cell is not present when the defective memory cell is not present.

5. The method of claim 4, wherein the selecting of whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory based on the defect information comprises determining not to select a memory cell of the defective column arranged in the row in which the spare memory cell storing ‘

1’

is present, when ‘

1’

is stored in the spare memory cell of the information storing spare column.

6. The method of claim 4, wherein the selecting of whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory based on the defect information comprises determining to select a memory cell of the defective column arranged in the row in which the spare memory cell storing ‘

0 is present, when ‘

0 is stored in the spare memory cell of the information storing spare column.

7. A method of improving an error checking and correction performance of a memory, the method comprising:

replacing a defective column including a defective memory cell of a memory cell array with a spare column of a spare cell array, wherein the memory cell array comprises memory cells in a matrix, and the spare cell array comprises spare memory cells in a matrix to be replaced for defective memory cells;

storing check bits of error correction code in at least one memory cell of at least one of a spare column that is not used to replace the defective column and the defective column;

storing defect information regarding the defective memory cell in a storage unit;

selecting whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and

performing error checking and correction on the memory using a memory cell selected based on a result of selecting whether the at least one memory cell storing the check bits is to be used.

8. The method of claim 7, wherein the defect information is address information of a defective row in which the defective memory cell is present.

9. The method of claim 8, wherein the selecting of whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory based on the defect information comprises determining not to select a memory cell of the defective column arranged in the defective row, the address information of which is stored in the storage unit.

10. The method of claim 8, wherein the storage unit is divided into regions identifying the defective column.

11. The method of claim 10, wherein the regions are divided from the storage unit, based on an original arrangement state of the spare column in the spare cell array before the spare column is used to replace the defective column.

12. The method of claim 11, wherein the defect information is capable of being stored in each of the regions of the storage unit.

13. The method of claim 12, wherein the selecting of whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory based on the defect information comprises selecting a memory cell of the defective column arranged in a normal row, the address information of which is not stored in the storage unit.

14. The method of claim 13, wherein the selecting of whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory based on the defect information comprises selecting a memory cell disposed between the memory cell array and the defective memory cell among memory cells of the defective column arranged in the defective row, the address information of which is stored in the storage unit.

15. The method of claim 7, wherein the storage unit is a content addressable memory (CAM).