VERTICAL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

• US 20160064541A1
• Filed: 08/29/2014
• Published: 03/03/2016
• Est. Priority Date: 08/29/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chih-Hao, Lien, Wai-Yi, DIAZ, Carlos H., Yang, Kai-Chieh, Tang, Hao-Ling
• Granted Patent: US 9,911,848 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source and a channel between the source and the drain. The gate surrounds a portion of the channel. The gate is configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor. In some embodiments, the vertical transistor further includes an ILD configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor.

Claims

1. A vertical transistor, comprising:

a source-channel-drain structure comprising a source, a drain over the source and a channel between the source and the drain;

a gate surrounding a portion of the channel, the gate being configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate being configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor; and

a gate dielectric layer between the channel and the gate.

2. The vertical transistor of claim 1, wherein the gate configured to provide the compressive strain substantially along the extending direction of the channel comprises titanium-aluminum (TiAl), titanium-aluminum carbide (TiAlC) or a combination thereof.

3. The vertical transistor of claim 1, wherein the gate configured to provide the tensile strain substantially along the extending direction of the channel comprises tungsten (W).

4. The vertical transistor of claim 1, further comprising an inter-layer dielectric (ILD) over the gate and in contact with the gate dielectric layer and surrounding another portion of the channel, and the ILD is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is the re-channel vertical transistor, or the ILD is configured to provide compressive strain substantially along the extending direction of the channel when the vertical transistor is the p-channel vertical transistor.

5. The vertical transistor of claim 4, wherein the drain has a width greater than a width of the channel.

6. The vertical transistor of claim 1, wherein the vertical transistor comprises a plurality of the source-channel-drain structures substantially parallel to one another.

7. A vertical transistor, comprising:

a source-channel-drain structure comprising a source, a drain over the source and a channel between the source and the drain;

a gate surrounding a portion of the channel;

a gate dielectric layer between the channel and the gate; and

an ILD over the gate and in contact with the gate dielectric layer and surrounding another portion of the channel, the ILD being configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the ILD being configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor.

8. The vertical transistor of claim 7, wherein the drain has a width greater than a width of the channel.

9. The vertical transistor of claim 8, wherein the width of the drain is greater than a bottom width of the drain.

10. The vertical transistor of claim 9, wherein a width difference between the width of the drain and the bottom width of the drain is lower than or equal to about 10 nm.

11. The vertical transistor of claim 7, wherein the drain has a bottom surface and an angled side surface surrounding the bottom surface, and an included angle between the bottom surface and the angled side surface is greater than 90-degrees and smaller than 180-degrees.

12. The vertical transistor of claim 11, wherein a height difference between a highest point of the angled side surface and a lowest point of the angled side surface is lower than or equal to about 30 nm.

13. The vertical transistor of claim 7, further comprising a spacer surrounds the drain.

14. The vertical transistor of claim 13, wherein the spacer has a thickness of about 2 to about 15 nm.

15. A method of manufacturing a vertical transistor, comprising:

forming a source-channel-drain structure, wherein the source-channel-drain structure comprises a source, a drain over the source and a channel between the source and the drain;

forming a gate dielectric layer surrounding the channel;

forming a gate surrounding a portion of the gate dielectric layer; and

forming an ILD over the gate and surrounding and in contact with another portion of the gate dielectric layer,

wherein the gate and the ILD are configured to independently or collectively provide strain substantially along an extending direction of the channel.

16. The method of claim 15, further comprising forming a spacer covering the drain before forming the gate dielectric layer surrounding the channel.

17. The method of claim 15, further comprising narrowing the channel when forming the gate dielectric layer surrounding the channel.

18. The method of claim 15, further comprising shrinking a bottom of the drain when forming the gate dielectric layer surrounding the channel.

19. The method of claim 15, wherein, when the vertical transistor is an n-channel vertical transistor, the gate is configured to provide compressive strain, or the ILD is configured to provide tensile strain, or the gate and the ILD are configured to respectively provide the compressive strain and the tensile strain.

20. The method of claim 15, wherein, when the vertical transistor is a p-channel vertical transistor, the gate is configured to provide tensile strain, or the ILD is configured to provide compressive strain, or the gate and the ILD are configured to respectively provide the tensile strain and the compressive strain.