PROCESS WINDOW IDENTIFIER

• US 20160085905A1
• Filed: 09/22/2015
• Published: 03/24/2016
• Est. Priority Date: 09/22/2014
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: CHEN, Frank Gang, DE VOCHT, Joseph Werner, DU, Yuelin, LI, Wanyu, LU, Yen-Wen
• Granted Patent: US 9,842,186 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70508 Data handling in all parts of the microlithographic apparatus, e.g. handling pattern data for addressable masks or data transfer to or from different components within the exposure apparatus
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G03F 7/70641 Focus
• CPC Class Codes: G03F 7/70666 Aerial image, i.e. measuring the image of the patterned exposure light at the image plane of the projection system
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed herein is a computer-implemented method for determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method comprising: obtaining a plurality of features in the area of interest; obtaining a plurality of values of one or more processing parameters of the device manufacturing process; determining existence of defects, probability of the existence of defects, or both in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and determining the OPW of the area of interest from the existence of defects, the probability of the existence of defects, or both.

Claims

1. A method of determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method comprising:

obtaining a plurality of features in the area of interest;

obtaining a plurality of values of one or more processing parameters of the device manufacturing process;

determining, by a computer system, an existence of a defect, probability of the existence of a defect, or both, in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and

determining, by the computer system, the OPW of the area of interest from the existence of a defect, the probability of the existence of a defect, or both.

2. The method of claim 1, wherein the plurality of features is selected based on data representing the design layout.

3. The method of claim 1, wherein the existence of a defect, the probability of the existence of a defect, or both, are determined from one or more characteristics of individual process windows (IPWs) of the plurality of features without actually determining the entire IPWs.

4. The method of claim 3, further comprising compiling the one or more characteristics into a map.

5. The method of claim 1, wherein the existence of a defect, the probability of the existence of a defect, or both, is determined from individual process windows (IPWs) of the plurality of features.

6. The method of claim 1, wherein the existence of a defect, the probability of the existence of a defect, or both, is determined using an empirical rule.

7. The method of claim 6, wherein the empirical rule is a classifier or a database.

8. The method of claim 7, wherein the classifier takes the plurality of values and one or more characteristics of the plurality of features as input and outputs the existence of a defect, the probability of the existence of a defect, or both.

9. The method of claim 8, wherein the classifier is selected from a group consisting of:

logistic regression and multinomial logit, probit regression, the perceptron algorithm, support vector machine, import vector machine, and linear discriminant analysis.

10. The method of claim 1, wherein the existence of a defect, the probability of the existence of a defect, or both, is determined using a computational model that calculates or simulates a portion or a characteristic of images of the plurality of features, and determines the existence of a defect, the probability of the existence of a defect, or both, from the portion or the characteristic.

11. The method of claim 1, wherein the existence of a defect, the probability of the existence of a defect, or both, is determined using experimental data obtained from a substrate inspection tool.

12. The method of claim 1, wherein the defect is selected from a group consisting of necking, line pull back, line thinning, critical dimension error, overlapping, resist top loss, resist undercut, and bridging.

13. The method of claim 1, wherein one or more of the one or more processing parameters are selected from a group consisting of:

focus, dose, a characteristic of an illumination source, a characteristic of projection optics, a characteristic of a resist, data obtained from metrology, data from an operator of a processing apparatus used in the device manufacturing process, a characteristic of development of the resist, a characteristic of post-exposure baking of the resist, and a characteristic of etching.

14. The method of claim 1, further comprising determining individual process windows (IPWs) of the plurality of features.

15. The method of claim 14, wherein determination of the OPW comprises overlapping the IPWs.

16. The method of claim 1, further comprising selecting a point in the OPW and conducting the device manufacturing process under values of the processing parameters represented by this point.

17. The method of claim 16, wherein the point is farthest from any boundary of the OPW.

18. The method of claim 1, wherein the plurality of features comprise a processing window limiting pattern (PWLP).

19. The method of claim 1, wherein the device manufacturing process involves using a lithography apparatus.

20. The method of claim 1, wherein the area of interest comprises a processing window limiting pattern (PWLP).

21. The method of claim 1, wherein the area of interest comprises two or more disconnected portions of the design layout.

22. The method of claim 1, wherein the area of interest is capable of being imaged concurrently onto the substrate by the device manufacturing process.

23. The method of claim 1, further comprising determining a global process window of the portion of the design layout from the OPW.

24. The method of claim 1, wherein at least one of the plurality of values is outside an individual process window (IPW) of at least one of the plurality of features.

25. The method of claim 1, wherein the plurality of values comprise a plurality of sets of values of a plurality of the processing parameters.

26. A non-transitory computer program product comprising a computer readable medium having instructions recorded thereon, the instructions when executed by a computer implementing the method of claim 1.