Ephemeral Storage Elements, Circuits, and Systems
First Claim
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1. A memory cell adapted with limited data retention capability for a data value and comprising:
- a charge storage element;
wherein said charge storage element is configured;
to store a first amount of charge corresponding to a first state representing a first data value; and
to store a second amount of charge corresponding to a second state representing a second data value;
said charge storage element being further configured to controllably leak charge over a predetermined period at a predetermined leakage rate, such that after being programmed from said first state to said second state by adding charge to said element, said charge storage element reverts to said first state over and before an end of said predetermined period;
wherein the memory cell is self-erasing and can be repeatedly reprogrammed from said first state to said second state by adding charge at the end of any of said predetermined periods.
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Abstract
An array of programmable non-volatile devices are is adapted such that their logic state is controllably altered over time by quiescent changes, slow controlled changes, scheduled changes, or some combination thereof imposed at a physical level. This allows for improved security and privacy for data to be permanently deleted. In some applications a data refresh and/or automatic backup can be implemented as well.
189 Citations
28 Claims
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1. A memory cell adapted with limited data retention capability for a data value and comprising:
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a charge storage element; wherein said charge storage element is configured; to store a first amount of charge corresponding to a first state representing a first data value; and to store a second amount of charge corresponding to a second state representing a second data value; said charge storage element being further configured to controllably leak charge over a predetermined period at a predetermined leakage rate, such that after being programmed from said first state to said second state by adding charge to said element, said charge storage element reverts to said first state over and before an end of said predetermined period; wherein the memory cell is self-erasing and can be repeatedly reprogrammed from said first state to said second state by adding charge at the end of any of said predetermined periods. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory device on an integrated circuit adapted with ephemeral data retention capability comprising:
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an array of charge storage elements; wherein each charge storage element in said array is configurable; to store a first amount of charge corresponding to a first state representing a first data value; and to store a second amount of charge corresponding to a second state representing a second data value; a programming control circuit configured; to program said array of charge storage elements to said second data value based on a first write operation; to initiate and control a slow erase operation on said array, including at least a first mode in which charge is removed from a selected charge storage element over a controlled predetermined period and in the absence of a new second write operation for such selected charge storage element. - View Dependent Claims (11, 12, 13)
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14. A memory device on an integrated circuit adapted with ephemeral data retention capability comprising:
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an array of charge storage elements; wherein said charge storage element is configurable; to store a first amount of charge corresponding to a first unprogrammed state representing a first data value; and to store a second amount of charge corresponding to a second programmed state representing a second data value; a programming control circuit configured; to set said array of charge elements to said second programmed state representing said second data value based on a first write operation; to initiate and control an erase operation on said array, including at least a first mode in which charge is removed from selected charge storage elements at predetermined erase periods and in the absence of a new second write operation for such array. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A nonvolatile memory cell circuit adapted with limited data access capability for a data value and comprising:
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a charge storage element; wherein said charge storage element is configurable; to store a first amount of charge corresponding to a first state representing a first data value; and to store a second amount of charge corresponding to a second state representing a second data value; a memory controller unit coupled to the charge storage element; said memory controller unit being configured to also remove data stored on the charge storage element as part of a read data access operation, such that after being programmed from said first to said second state by adding charge to said element, said charge storage element is changeable to said first state as part of said read data access operation. - View Dependent Claims (22, 23, 24, 25)
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26. A system for storing data files on a physical medium in accordance with programmable data retention periods specified for such data files comprising:
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a controller for receiving and processing a first target data retention period specified by a user for a first user data file; a storage device configured for storing said first data file on said physical medium under control of said controller such that it is retained physically on such storage device only during said first target data retention period; wherein said storage device is adapted such that a physical state of such physical medium device can be substantially changed during a quiescent operational state for such device, and such that at the end of said first target data retention period, data for said data file also can be substantially changed.
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27. A limited retention period digital loop memory device comprising:
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a memory circuit adapted to be partitioned into N separate limited retention data recordable portions, including a 1st memory portion and a 2nd memory portion; wherein each of said 1st and 2nd limited retention data recordable portions is adapted to store programmed data only for a first limited period of time, after which time such data returns to a non-programmed state; a controller circuit for writing said programmed data to the N separate recordable portions of the memory circuit, including a first set of data for the 1st memory portion and a second set of data for said 2nd memory portion, during a master programming cycle; where said controller circuit is configured to write said first set of data and said second set of data at different times of the master programming cycle, such that said 1st memory portion is programmed at a first time, and said 2nd memory portion is programmed at a second time; and further wherein said controller circuit re-programs said 1st memory portion with a third set of data only after said first limited period of time has expired and said first set of data has returned to an unprogrammed state in said 1st memory portion.
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28. A self-erasing file storage system comprising:
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a data storage device adapted to store file data, including a first data file for a user; a file key generator adapted to create a first public key and a first private key for a first data file; an access controller adapted to read and write said first data filed based on said first public key and said first private key; a private key storage device adapted to store at least said first private key; an ephemeral memory incorporated as part of least one of said data storage device and said private key storage device; wherein said ephemeral memory portion is self-erasing in a quiescent state and effectuates a controllable limited data retention memory for storing said first file data and/or said first private key.
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Specification