Addressing, Command Protocol, and Electrical Interface for Non-volatile Memories Utilized in Recording Usage Counts

• US 20160111137A1
• Filed: 12/28/2015
• Published: 04/21/2016
• Est. Priority Date: 06/16/2005
• Status: Active Grant

• Current Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Original Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Inventors: Booth, James Ronald
• Granted Patent: US 9,837,136 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module, including a plurality of memory cells and a plurality of signal lines for communicating with a processing device. The memory module is configured such that following reception of a command and upon encountering a first condition while processing the command, the memory module limits a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time for indicating an occurrence of the first condition.

Claims

1. A memory module, comprising:

a plurality of memory cells; and

a plurality of signal lines for communicating with a processing device, the memory module configured such that upon encountering a busy condition while processing a command received by the memory module, the memory module limits a voltage on a first signal line of the plurality of signal lines for a period of time to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state when voltages on the first signal line is not limited by the memory module, for indicating an occurrence of the busy condition,

wherein the memory module is configured to receive a clock signal on the first signal line, and during the period of time in which the memory modules limits a voltage on the first signal line of the plurality of signal lines to be no more than the intermediate voltage, the memory module

     1) receives the clock signal on the first signal line and

     2) at the same time indicates to the processing device the occurrence of the busy condition by limiting the voltage on the first signal line to be no more than the intermediate voltage.

2. The memory module of claim 1, wherein upon encountering an error condition while processing the command, the memory module limits a voltage on a second signal line of the plurality of signal lines for a second period of time to be no more than a second intermediate voltage greater than voltage levels corresponding to the binary zero state and less than voltage levels corresponding to the binary one state when voltages on the second signal line is not limited by the memory module, for indicating to the processing device an occurrence of the error condition, wherein the memory module is configured to receive a second signal on the second signal line, and during the second period of time the memory module limits the voltage on the second signal line to be no greater than the second intermediate voltage, the memory module receives the second signal on the second signal line while at the same time the memory module indicates to the processing device the occurrence of the error condition on the second signal line by limiting the voltage on the second signal line to be no more than the second intermediate voltage, and wherein the second signal comprises an address-data signal.

3. The memory module of claim 2, further comprising at least one electrical component coupled between the second signal line and a reference potential such that the second intermediate voltage during the second period of time is based upon at least one of a voltage across and a current passing through the at least one electrical component.

4. The memory module of claim 2, wherein the second intermediate voltage is the same as the intermediate voltage.

5. The memory module of claim 1, further comprising at least one electrical component coupled between the first signal line and a reference potential such that the intermediate voltage during the period of time is based upon at least one of a voltage across and a current passing through the at least one electrical component.

6. The memory module of claim 5, wherein the intermediate voltage is based at least in part upon a resistance of the at least one electrical component.

7. The memory module of claim 5, wherein the at least one electrical component comprises at least one resistor.

8. The memory module of claim 3, wherein the at least one electrical component comprises at least one diode.

9. A memory device, comprising:

a first signal line for receiving, by the memory device, a clock input signal;

a second signal line for communicating address and data information; and

a plurality of memory cells and circuitry coupled to the first signal line and the second signal line, the circuitry limiting a voltage level on the first signal line for a first period of time to be no more than a first voltage level in response to encountering a busy condition by the memory device during processing of a command, the first voltage level being less than voltage levels corresponding to a binary one state when voltages on the first signal line are not limited by the circuitry and greater than voltage levels corresponding to a binary zero state,

wherein during the first period of time, the memory device receives the clock input signal on the first signal line from a processing device while at the same time the memory device communicates to the processing device an occurrence of the busy condition by limiting the voltage of the clock input signal to be no more than the first voltage level.

10. The memory device of claim 9, wherein the circuitry limits a voltage level on the second signal line for a second period of time to be no more than a second voltage level less than the voltage levels corresponding to the logic one state when voltages on the second signal line are not limited by the circuitry and greater than voltages corresponding to the logic zero state in response to encountering an error condition by the memory device during processing of the command, and wherein during the second period of time, the memory device receives a second input signal on the second signal line from the processing device while at the same time communicates to the processing device the occurrence of the error condition of the memory device by limiting the voltage of the second input signal to be no more than the second voltage level.

11. The memory device of claim 10, wherein the second voltage level is the same as the first voltage level.

12. The memory device of claim 10, wherein the circuitry includes at least one electrical component disposed between the second signal line and a voltage reference, wherein the second voltage level on the second signal line during the second period of time is based at least in part upon the at least one electrical component.

13. The memory device of claim 9, wherein the circuitry comprises at least one electrical component disposed between the first signal line and a voltage reference, wherein the first voltage level on the first signal line during the first period of time is based at least in part upon the at least one electrical component.

14. The memory device of claim 9, wherein the circuitry comprises at least one electrical component disposed between the first signal line and voltage reference, wherein the first voltage level on the first signal line during the first period of time is based at least in part upon at least one of a voltage across and a current passing through the at least one electrical component.

15. The memory device of claim 14, wherein the at least one electrical component comprises at least one of a diode and a resistor.

16. A memory device, comprising:

a first signal line for receiving, by the memory device, a clock input signal;

a second signal line for communicating address and data information; and

a plurality of memory cells and circuitry coupled to the first signal line and the second signal line, the circuitry setting an upper voltage level on the first signal line for a first period of time to a first voltage level in response to encountering a busy condition by the memory device during processing of a command, the first voltage level being greater than voltage levels corresponding to a binary one state when upper voltage levels on the first signal line are not set by the circuitry, wherein during the first period of time, the memory device receives the clock input signal on the first signal line from a processing device while at the same time the memory device communicates to the processing device an occurrence of the busy condition by setting the upper voltage of the clock input signal to be the first voltage level.