SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

• US 20160111516A1
• Filed: 10/15/2015
• Published: 04/21/2016
• Est. Priority Date: 10/16/2014
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: HONG, ZHONGSHAN
• Granted Patent: US 9,761,716 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces of each first opening. Second openings corresponding to the first openings are formed through the insulating layer and into the substrate. The sidewall surfaces of the substrate in the second openings are etched to define a second distance between adjacent substrate sidewalls of adjacent etched second openings. The second distance is shorter than the first distance. An isolation layer is formed in the first and second openings. Conductive structures are formed on the semiconductor layer on both sides of a gate structure formed on the semiconductor layer. The conductive structures penetrate through the isolation layer and into the substrate.

Claims

1. A method for forming a semiconductor device, comprising:

providing a stacked substrate including a substrate, an insulating layer on a surface of the substrate, a semiconductor layer on a surface of the insulating layer;

forming a plurality of first openings in the semiconductor layer to expose the insulating layer at a bottom surface of the plurality of first openings, wherein a first distance is defined between adjacent sidewalls of adjacent first openings;

forming spacers on sidewall surfaces of each first opening in the semiconductor layer;

etching the insulating layer and the substrate through the bottom surface of each first opening employing the semiconductor layer and the spacers as an etch mask to form a plurality of second openings through the insulating layer and into the substrate;

etching sidewall surfaces of the substrate exposed in the second openings to define a second distance between adjacent substrate sidewalls of adjacent etched second openings, wherein the second distance is shorter than the first distance;

forming an isolation layer in the plurality of second openings and the plurality of first openings;

forming a gate structure on a surface portion of the semiconductor layer between adjacent isolation layers; and

forming conductive structures on surface portions of the semiconductor layer on both sides of the gate structure, wherein the conductive structures penetrate through the isolation layer and into the substrate of the stacked substrate.

2. The method according to claim 1, wherein the stacked substrate is a semiconductor-on-insulator substrate having an ultra-thin body as the semiconductor layer and a buried oxide as the insulating layer of the stacked substrate.

3. The method according to claim 1, wherein the semiconductor layer has a thickness between about 5 Å

and about 20 Å and

the insulating layer has a thickness between about 5 Å and

about 40 Å

.

4. The method according to claim 1, wherein the step of forming the conductive structures includes:

forming a dielectric layer on the isolation layer, the semiconductor layer and the gate structure;

etching the dielectric layer to expose the surface portions of the semiconductor layer on both sides of the gate structure;

forming through-holes in the dielectric layer; and

filling the through-holes with a conductive material to form the conductive structures.

5. The method according to claim 4, wherein the through-holes also expose a portion of the isolation layer, and a bottom part of the conductive structures is located on a surface of the isolation layer or inside the isolation layer.

6. The method according to claim 5, wherein the bottom part of the conductive structures extend into the isolation layer and under a top surface of the substrate.

7. The method according to claim 1, wherein the step of forming the first openings includes:

forming a mask layer on the semiconductor layer to expose surface portions of the semiconductor layer corresponding to the first openings to be formed; and

using the mask layer as an etch mask to etch the semiconductor layer until the insulating layer is exposed to form the first openings.

8. The method according to claim 7, wherein the mask layer is removed after the substrate sidewalls exposed in the second openings are etched.

9. The method according to claim 8, wherein the step for forming the spacers includes:

forming a sidewall film on the mask layer and on sidewall surfaces and bottom surfaces of the first openings;

etching back the sidewall film to expose the mask layer and a surface portion of the insulating layer at the bottom of the first openings to form the spacers on the sidewall surfaces of the first openings and on another surface portion of the insulating layer.

10. The method according to claim 1, wherein the spacers are made of a material including one or more of silicon oxide, silicon nitride, silicon oxynitride, polysilicon, and amorphous carbon.

11. The method according to claim 1, wherein the isotropic etching process is used when the substrate sidewalls exposed in the second openings are etched.

12. The method according to claim 1, wherein the step of etching the sidewall surfaces of the substrate exposed in the second openings includes an anisotropic dry etching process, such that sidewalls of the etched second openings are formed perpendicular to the surface of the substrate.

13. The method according to claim 1, wherein the step of forming the isolation layer includes:

forming an isolation film in the second openings and the first openings and on the semiconductor layer to fill up the second openings and the first openings; and

planarizing the isolation film until the semiconductor layer is exposed to form the isolation layer.

14. The method according to claim 1, wherein the gate structure includes:

a gate dielectric layer on the semiconductor layer;

a gate electrode layer on the gate dielectric layer; and

gate sidewall spacers on sidewall surfaces of the gate dielectric layer and the gate electrode layer.

15. The method according to claim 1, further including:

forming a source region and a drain region in the semiconductor layer on both sides of the gate structure before forming the conductive structures, wherein the conductive structures are located on the source region and the drain region.

16. The method according to claim 1, further including:

removing the spacers in the first openings prior to forming the isolation layer.

17. A semiconductor device, comprising:

a stacked substrate, including a substrate, an insulating layer on a surface of the substrate, and a semiconductor layer on a surface of the insulating layer,

wherein the semiconductor layer includes a plurality of first openings therein to expose the insulating layer and to provide a first distance between adjacent sidewalls of adjacent first openings, and

wherein the stacked substrate further includes a plurality of second openings located through the insulating layer and into the substrate at a bottom of the plurality of first openings, and wherein sidewalls of the substrate in the plurality of second openings are recessed with respect to sidewalls of the semiconductor layer in the plurality of first openings, and a second distance is defined between adjacent substrate sidewalls of adjacent second openings, the second distance being shorter than the first distance;

an isolation layer located in the plurality of second openings and the plurality of first openings;

a gate structure on a surface portion of the semiconductor layer between adjacent isolation layers; and

conductive structures on surface portions of the semiconductor layer on both sides of the gate structure, wherein the conductive structures penetrate through the isolation layer and into the substrate of the stacked substrate.

18. The device according to claim 17, wherein:

the stacked substrate is a semiconductor-on-insulator substrate having an ultra-thin body as the semiconductor layer and a buried oxide as the insulating layer of the stacked substrate,

the semiconductor layer has a thickness between about 5 Å and

about 20 Å

, and

the insulating layer has a thickness between about 5 Å and

about 40 Å

.

19. The device according to claim 17, wherein:

the conductive structures have a bottom part located on a surface of the isolation layer or inside the isolation layer, and

the bottom part of the conductive structures penetrate through the isolating layer of the stacked substrate and into a top surface of the substrate.

20. The device according to claim 17, further including spacers on the sidewall surfaces of the semiconductor layer in the first openings.