SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20160111546A1
• Filed: 10/15/2015
• Published: 04/21/2016
• Est. Priority Date: 10/17/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: TEZUKA, Sachiaki, TANAKA, Tetsuhiro, TAKEUCHI, Toshihiko, SUZAWA, Hideomi, HONDO, Suguru
• Granted Patent: US 9,660,098 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.

Claims

1. (canceled)

2. A semiconductor device comprising:

an oxide stack comprising;

an oxide layer; and

an oxide semiconductor layer over the oxide layer, wherein an electron affinity of the oxide semiconductor layer is higher than an electron affinity of the oxide layer by 0.1 eV or more;

a gate insulating layer in contact with the oxide stack; and

a gate electrode layer overlapping with the oxide stack with the gate insulating layer there between,

wherein a spin density corresponding to a signal at a g-factor of greater than or equal to 1.90 and less than or equal to 1.95 is 1.5×

10¹² spins/cm² or less and a spin density corresponding to a signal at a g-factor of greater than or equal to 2.00 and less than or equal to 2.01 is 2×

10¹² spins/cm² or more in electron spin resonance spectroscopy.

3. The semiconductor device according to claim 2,

wherein the oxide semiconductor layer and the oxide layer comprise indium, and

wherein a proportion of indium in the oxide semiconductor layer is higher than a proportion of indium in the oxide layer.

4. The semiconductor device according to claim 2, wherein the oxide semiconductor layer and the oxide layer comprise indium, gallium, and zinc.

5. The semiconductor device according to claim 2, wherein the oxide semiconductor layer comprises a crystal whose c-axis is aligned in a direction substantially perpendicular to an upper surface of the oxide semiconductor layer.

6. The semiconductor device according to claim 2, wherein a concentration of silicon in the oxide semiconductor layer is lower than 2×

10¹⁸ atoms/cm³.

7. The semiconductor device according to claim 2,

wherein the gate insulating layer is provided over the oxide stack, and

wherein the gate electrode layer is provided over the gate insulating layer.

8. A semiconductor device comprising:

a base insulating layer;

an oxide stack comprising;

an oxide layer over the base insulating layer; and

an oxide semiconductor layer over the oxide layer, wherein an electron affinity of the oxide semiconductor layer is higher than an electron affinity of the oxide layer by 0.1 eV or more;

a source electrode layer and a drain electrode layer in contact with the oxide stack;

a gate insulating layer over the source electrode layer and the drain electrode layer;

a gate electrode layer over the gate insulating layer; and

an interlayer insulating layer over the gate electrode layer,

wherein the oxide semiconductor layer has a spin density of 1.5×

10¹⁸ spins/cm² or less corresponding to a signal at a g-factor of greater than or equal to 1.90 and less than or equal to 1.95 in electron spin resonance spectroscopy, and

wherein the gate insulating layer has a spin density of 2×

10¹⁸ spins/cm² or more corresponding to a signal at a g-factor of greater than or equal to 2.00 and less than or equal to 2.01 in electron spin resonance spectroscopy.

9. The semiconductor device according to claim 8,

wherein the oxide semiconductor layer and the oxide layer comprise indium, and

wherein a proportion of indium in the oxide semiconductor layer is higher than a proportion of indium in the oxide layer.

10. The semiconductor device according to claim 8, wherein the oxide semiconductor layer and the oxide layer comprise indium, gallium, and zinc.

11. The semiconductor device according to claim 8, wherein the oxide semiconductor layer comprises a crystal whose c-axis is aligned in a direction substantially perpendicular to an upper surface of the oxide semiconductor layer.

12. The semiconductor device according to claim 8, wherein a concentration of silicon in the oxide semiconductor layer is lower than 2×

10¹⁸ atoms/cm³.

13. The semiconductor device according to claim 8, wherein each of the source electrode layer and the drain electrode layer has a stepped shape in a periphery portion thereof.

14. The semiconductor device according to claim 8, wherein each of the source electrode layer and the drain electrode layer comprises a first electrode layer and a second electrode layer over the first electrode layer.

15. A semiconductor device comprising:

an oxide stack comprising;

a first oxide layer;

an oxide semiconductor layer over the first oxide layer; and

a second oxide layer over the oxide semiconductor layer, wherein an electron affinity of the oxide semiconductor layer is higher than an electron affinity of the first oxide layer or the second oxide layer by 0.1 eV or more;

a source electrode layer and a drain electrode layer in contact with the oxide stack;

a gate insulating layer in contact with the oxide stack; and

a gate electrode layer overlapping with the oxide stack with the gate insulating layer there between,

wherein the oxide semiconductor layer has a spin density of 1.5×

10¹⁸ spins/cm² or less corresponding to a signal at a g-factor of greater than or equal to 1.90 and less than or equal to 1.95 in electron spin resonance spectroscopy, and

wherein the gate insulating layer has a spin density of 2×

10¹⁸ spins/cm² or more corresponding to a signal at a g-factor of greater than or equal to 2.00 and less than or equal to 2.01 in electron spin resonance spectroscopy.

16. The semiconductor device according to claim 15,

wherein the oxide semiconductor layer, the first oxide layer, and the second oxide layer comprise indium, and

wherein a proportion of indium in the oxide semiconductor layer is higher than a proportion of indium in the first oxide layer or the second oxide layer.

17. The semiconductor device according to claim 15, wherein the oxide semiconductor layer, the first oxide layer, and the second oxide layer comprise indium, gallium, and zinc.

18. The semiconductor device according to claim 15, wherein the oxide semiconductor layer comprises a crystal whose c-axis is aligned in a direction substantially perpendicular to an upper surface of the oxide semiconductor layer.

19. The semiconductor device according to claim 15, wherein a concentration of silicon in the oxide semiconductor layer is lower than 2×

10¹⁸ atoms/cm³.

20. The semiconductor device according to claim 15, wherein each of the source electrode layer and the drain electrode layer has a stepped shape in a periphery portion thereof.

21. The semiconductor device according to claim 15, wherein each of the source electrode layer and the drain electrode layer comprises a first electrode layer and a second electrode layer over the first electrode layer.

22. The semiconductor device according to claim 15,

wherein the gate insulating layer is provided over the oxide stack, and

wherein the gate electrode layer is provided over the gate insulating layer.