Low Power Automatic Calibration Method for High Frequency Oscillators

• US 20160112052A1
• Filed: 10/09/2015
• Published: 04/21/2016
• Est. Priority Date: 10/20/2014
• Status: Active Grant

• Current Assignee: Ambiq Micro, Inc.
• Original Assignee: Ambiq Micro, Inc.
• Inventors: Sheafor, Stephen James
• Granted Patent: US 9,939,839 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 19/0084 measuring voltage only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3041 where the computing system component is an input/output interface interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: G06F 11/3414 Workload generation, e.g. scripts, playback
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/181 a numerical count result being used for locking the loop, the counter counting during fixed time intervals H03L7/1806 takes precedence
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A clock calibrator for use in an electronic system comprising an integrated circuit such as a microcontroller. The clock calibrator embodies a frequency adjustment facility adapted dynamically to adjust the frequency of one or more high-frequency clock generators as a function of a lower-frequency reference clock.

Claims

1. A clock calibration method comprising the steps of:

[1] in response to a first control signal;

[1.1] in response to a second control signal, selectively enabling a reference clock oscillator to develop reference clock pulses at a selected reference frequency; and

[1.2] in response to a third control signal, selectively enabling a measured clock oscillator to develop measured clock pulses at a frequency determined as a function of an adjustment value;

[2] in response to a first one of the reference clock pulses, initiating counting of the measured clock pulses;

[3] in response to a second reference clock pulse, terminating counting of the measured clock pulses; and

[4] adjusting the adjustment value as a function of a difference between the count of the measured clock pulses and a selected target value.

2. The method of claim 1 further comprising the step of:

[5] selectively repeating steps [2] through [4].

3. The method of claim 1 or claim 2 further comprising the steps of:

[6] in response to the second control signal, selectively disabling the reference clock oscillator; and

[7] in response to the third control signal, selectively disabling the measured clock oscillator.

11. A clock calibration facility configured to perform the method of any preceding claim.

12. An electronic system comprising a clock calibration facility according to claim 11.

4. A clock calibration method comprising the steps of:

[1] in response to a first control signal;

[1.1] in response to a second control signal, selectively enabling a reference clock oscillator to develop reference clock pulses at a selected reference frequency; and

[1.2] in response to a third control signal, selectively enabling a measured clock oscillator to develop measured clock pulses at a frequency determined as a function of an adjustment value; and

[2] in response to a selected one of the reference clock pulses, adjusting the adjustment value as a function of a difference between the frequency of the measured clock relative to the frequency of the reference clock.

5. The method of claim 4 further comprising the step of:

[3] selectively repeating step [2].

6. The method of claim 4 or claim 5 further comprising the steps of:

[4] in response to the second control signal, selectively disabling the reference clock oscillator; and

[5] in response to the third control signal, selectively disabling the measured clock oscillator.

7. A clock calibration method comprising the steps of:

[1] in response to a first control signal, selectively enabling a reference clock oscillator to develop reference clock pulses at a selected reference frequency;

[2] in response to a second control signal, selectively enabling a measured clock oscillator to develop measured clock pulses at a frequency determined as a function of an adjustment value;

[3] in response to a first one of the reference clock pulses, initiating counting of the measured clock pulses;

[4] in response to a second reference clock pulse, terminating counting of the measured clock pulses;

[5] adjusting the adjustment value as a function of a difference between the count of the measured clock pulses and a selected target value;

[6] selectively repeating steps [3] through [5];

[7] in response to the first control signal, selectively disabling the reference clock oscillator; and

[8] in response to the second control signal, selectively disabling the measured clock oscillator.

9. The method of claim 7 further comprising the step of:

[4] selectively repeating step [3].

10. The method of claim 7 or claim 8 further comprising the steps of:

[5] in response to the second control signal, selectively disabling the reference clock oscillator; and

[6] in response to the third control signal, selectively disabling the measured clock oscillator.

8. A clock calibration method comprising the steps of:

[1] in response to a first control signal, selectively enabling a reference clock oscillator to develop reference clock pulses at a selected reference frequency;

[2] in response to a second control signal, selectively enabling a measured clock oscillator to develop measured clock pulses at a frequency determined as a function of an adjustment value; and

[3] in response to a selected one of the reference clock pulses, adjusting the adjustment value as a function of a difference between the frequency of the measured clock relative to the frequency of the reference clock.