ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, AND DISPLAY DEVICE

• US 20160126261A1
• Filed: 07/17/2015
• Published: 05/05/2016
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: LIU, Chong, ZHAO, Haisheng, MA, Haitao, XIAO, Hongxi, PENG, Zhilong, LIU, Huanping
• Granted Patent: US 9,711,539 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting

Abstract

The present invention provides an array substrate, a method of fabricating the array substrate, and a display device. The method of fabricating the array substrate of the present invention comprises steps of: sequentially forming a first transparent conductive film and a source-drain metal film on a substrate; forming a source-drain metal pattern by performing a patterning process on the source-drain metal film; forming a pattern comprising a pixel electrode and a compensation structure that is provided below the source-drain metal pattern by performing a patterning process on the first transparent conductive film.

Claims

1. A method of fabricating an array substrate, comprising steps of:

sequentially forming a first transparent conductive film and a source-drain metal film on a substrate;

forming a source-drain metal pattern by performing a patterning process on the source-drain metal film; and

forming a pattern comprising a pixel electrode and a compensation structure that is provided below the source-drain metal pattern by performing a patterning process on the first transparent conductive film.

2. The method of claim 1, wherein the source-drain metal pattern comprises at least a source, a drain, and a data line.

3. The method of claim 2, wherein before forming the first transparent conductive film, the method further comprises steps of:

forming a gate metal pattern through a patterning process;

forming a gate insulation layer; and

forming a pattern comprising an active layer through a patterning process.

4. The method of claim 3, wherein when the active layer is formed, an ohmic contact pattern is further formed to cover the active layer.

5. The method of claim 4, wherein after forming the pattern comprising the pixel electrode and the compensation structure, the method further comprises steps of:

removing the ohmic contact pattern provided between the source and the drain and provided above an active region of the active layer through dry etching, so as to form an ohmic contact layer,

wherein the source and the drain are electrically connected to the active layer through the ohmic contact layer, respectively.

6. The method of claim 5, wherein after forming the ohmic contact layer, the method further comprises steps of:

forming a planarization layer; and

forming a pattern comprising a common electrode through a patterning process.

7. The method of claim 3, wherein the gate metal pattern comprises at least a gate, a gate line, and a gate metal connecting line.

8. An array substrate, comprising:

a pixel electrode and a compensation structure provided in the same layer above a substrate, the compensation structure comprising transparent conductive material; and

a source-drain metal pattern provided on the compensation structure.

9. The array substrate of claim 8, wherein the source-drain metal pattern comprises at least a source, a drain, and a data line.

10. The array substrate of claim 9, wherein between the substrate and the pixel electrode, the array substrate further comprises:

a gate metal pattern provided above the substrate;

a gate insulation layer provided on the gate metal pattern; and

an active layer provided on the gate insulation layer.

11. The array substrate of claim 10, further comprising an ohmic contact layer provided on the active layer, wherein the source and the drain are electrically connected to the active layer through the ohmic contact layer, respectively.

12. The array substrate of claim 11, further comprising:

a planarization layer; and

a common electrode provided on the planarization layer.

13. The array substrate of claim 10, wherein the gate metal pattern comprises at least a gate, a gate line, and a gate metal connecting line.

14. A display device, comprising an array substrate, the array substrate comprising:

a pixel electrode and a compensation structure provided in the same layer above a substrate, the compensation structure comprising transparent conductive material; and

a source-drain metal pattern provided on the compensation structure.

15. The display device of claim 14, wherein the source-drain metal pattern comprises at least a source, a drain, and a data line.

16. The display device of claim 15, wherein between the substrate and the pixel electrode, the array substrate further comprises:

a gate metal pattern provided above the substrate;

a gate insulation layer provided on the gate metal pattern; and

an active layer provided on the gate insulation layer.

17. The display device of claim 16, further comprising an ohmic contact layer provided on the active layer, wherein the source and the drain are electrically connected to the active layer through the ohmic contact layer, respectively.

18. The display device of claim 17, further comprising:

a planarization layer; and

a common electrode provided on the planarization layer.

19. The display device of claim 16, wherein the gate metal pattern comprises at least a gate, a gate line, and a gate metal connecting line.