NON MAIN CPU/OS BASED OPERATIONAL ENVIRONMENT
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Abstract
A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
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Citations
32 Claims
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1-12. -12. (canceled)
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13. An apparatus comprising:
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a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices; a power manager to put the microcontroller into a sleep state to save power; and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state, wherein the microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. At least one non-transitory machine accessible storage medium having code stored thereon, wherein the code when executed on a machine, causes the machine to:
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put a microcontroller into a sleep state to save power, wherein the microcontroller is to facilitate data communication within a system comprising a plurality of peripheral devices; enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state; receive at least one signal from a component of the system external to the microcontroller; cause the microcontroller to wake from the sleep state in response to the at least one signal, wherein communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.
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24. A system comprising:
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a plurality of peripheral devices; a microcontroller to facilitate data communication between at least a portion of the plurality of peripheral devices; a power manager to put the microcontroller into a sleep state to save power; and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state, wherein the microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32)
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Specification