Memory Wear Leveling

• US 20160139826A1
• Filed: 11/13/2014
• Published: 05/19/2016
• Est. Priority Date: 11/13/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Fontana, Marco Giovanni, Montanaro, Massimo
• Granted Patent: US 9,830,087 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second sector; and re-ordering a position of at least one sub-sector of the first sector, the second sector, or both.

Claims

1. A memory device, comprising:

a memory array of sectors having one or more sub-sectors;

a controller configured to receive, transmit, or receive and transmit data via a peripheral interface bus, wherein the controller comprises wear-leveling logic configured to;

detect a high wear sub-sector of the memory device having a high wear level, the sub-sector residing in a first sector;

determine a second sector of the memory device having a low wear level;

swap the first sector with the second sector; and

re-order a position of at least one sub-sector of the first sector, the second sector, or both.

2. The memory device of claim 1, wherein the wear-leveling logic is configured to re-order the position of the at least one sub-sector while swapping the first sector with the second sector.

3. The memory device of claim 1, wherein the wear-leveling logic is configured to:

determine a minimum sub-sector of the second sector having a minimum wear level;

re-order the position of the high wear sub-sector by swapping the position of the high wear sub-sector with a position of the minimum sub-sector.

4. The memory device of claim 1, wherein the wear-leveling logic is configured to:

bundle all sub-sectors of the first sector into a first set of sub-sector bundles;

bundle all sub-sectors of the second sector into a second set of sub-sector bundles; and

swap a position of a first bundle containing the high wear sub-sector with a position of a second bundle containing the minimum sub-sector.

5. The memory device of claim 1, wherein the memory device comprises a NAND type flash memory device.

6. The memory device of claim 1, wherein the memory device comprises a NOR type flash memory device.

7. The memory device of claim 1, comprising:

rescrambling logic configured to modify one or more intra-sector addresses of the memory array; and

a block mapping unit configured to re-map one or more sectors, one or more sub-sectors, or both of the memory-array, wherein the block mapping unit is configured to provide configuration bits to the rescrambling logic to enable the modification of the one or more intra-sector addresses;

wherein the rescrambling logic is used to re-order the position of the at least one sub-sector of the first sector, the second sector, or both.

8. The memory device of claim 7, wherein the rescrambling logic comprises a multiplexer (MUX);

wherein the configuration bits comprise a plurality of sets of bits, each set of bits representing an address modification; and

wherein the MUX is configured to select one of the plurality of sets of bits, the selection resulting in an address modification represented by the selected one of the plurality of sets of bits.

9. The memory device of claim 7, wherein the rescrambling logic comprises combinational logic;

wherein the configuration bits comprise a single set of configuration bits; and

wherein the combinational logic affects a modification to an intra-sector address using the single set of configuration bits.

10. The memory device of claim 9, wherein the combinational logic comprises summation combinational logic.

11. The memory device of claim 9, wherein the combinational logic comprises exclusive or (XOR) combinational logic.

12. A method, comprising:

detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector;

determining a second sector of the memory device having a low wear level;

swapping the first sector with the second sector; and

re-ordering a position of at least one sub-sector of the first sector, the second sector, or both.

13. The method of claim 12, comprising:

determining a minimum sub-sector of the second sector having a minimum wear level; and

re-ordering the position of the high wear sub-sector by swapping the position of the high wear sub-sector with a position of the minimum sub-sector.

14. The method of claim 12, comprising:

bundling all sub-sectors of the first sector into a first set of sub-sector bundles;

bundling all sub-sectors of the second sector into a second set of sub-sector bundles; and

swapping a position of a first bundle containing the high wear sub-sector with a position of a second bundle containing the minimum sub-sector.

15. The method of claim 12, comprising:

modifying one or more intra-sector addresses of the memory array to re-order the position of the at least one sub-sector of the first sector, the second sector, or both.

16. The method of claim 15, comprising modifying the one or more intra-sector addresses of the memory array using a multiplexer.

17. The method of claim 15, comprising modifying the one or more intra-sector addresses of the memory array using combinational logic comprising summation logic, exclusive or (XOR) logic, or both.

18. A tangible, non-transitory, machine-readable medium, comprising instructions to:

detect, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector;

determine a second sector of the memory device having a low wear level;

swap the first sector with the second sector; and

re-order a position of at least one sub-sector of the first sector, the second sector, or both, by;

swapping a position of the high wear sub-sector with a position of a low wear sub- sector in the second sector;

modifying one or more intra-sector addresses of the first sector, the second sector, or both;

or

both.

19. The machine-readable medium of claim 18, comprising instructions to swap the position of the high wear sub-sector with the position of the low wear sub-sector in the minimum sub-sector by:

bundling all sub-sectors of the first sector into a first set of sub-sector bundles;

bundling all sub-sectors of the second sector into a second set of sub-sector bundles; and

swapping a position of a first bundle containing the high wear sub-sector with a position of a second bundle in the second sector containing the low wear sub-sector.

20. The machine-readable medium of claim 18, comprising instructions to modify the one or more intra-sector addresses of the first sector, the second sector, or both by:

using a multiplexer to select one or more modifications to the one or more intra-sector addresses;

using combinational logic to make one or more modifications to the one or more intra-sector addresses;

or

both.

21. A memory controller, comprising:

circuitry configured to;

detect a high wear sub-sector of a memory device having a high wear level, the sub-sector residing in a first sector;

determine a second sector of the memory device having a low wear level;

swap the first sector with the second sector; and

re-order a position of at least one sub-sector of the first sector, the second sector, or both.

22. The memory controller of claim 21, wherein the circuitry is configured to re-order the position of the at least one sub-sector while swapping the first sector with the second sector.

23. The memory controller of claim 21, wherein the circuitry is configured to:

determine a minimum sub-sector of the second sector having a minimum wear level;

re-order the position of the high wear sub-sector by swapping the position of the high wear sub-sector with a position of the minimum sub-sector.

24. The memory controller of claim 21, wherein the circuitry is configured to:

bundle all sub-sectors of the first sector into a first set of sub-sector bundles;

bundle all sub-sectors of the second sector into a second set of sub-sector bundles; and

swap a position of a first bundle containing the high wear sub-sector with a position of a second bundle containing the minimum sub-sector.

25. The memory controller of claim 21, wherein the circuitry is configured to:

modify one or more intra-sector addresses of a memory array to re-order the position of the at least one sub-sector of the first sector, the second sector, or both.

26. A memory system, comprising:

a slave device configured to manage, store, or manage and store data;

a master device configured to provide data frames to the slave device to facilitate the management, storage, or the management and storage of the data;

a peripheral interface configured to communicatively couple the master device with the slave device, wherein the data frames are provided from the master device to the slave device via the peripheral interface;

wear logic configured to;

detect, in the slave device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector;

determine, in the slave device, a second sector having a low wear level;

swap the first sector with the second sector; and

re-order a position of at least one sub-sector of the first sector, the second sector, or both.

27. The memory system of claim 26, wherein the wear logic is contained within a controller of the slave device.

28. The memory system of claim 26, wherein the wear logic is contained at least in part in the master device.

30. The memory system of claim 26, wherein the wear logic is configured to:

modify one or more intra-sector addresses of a memory array to re-order the position of the at least one sub-sector of the first sector, the second sector, or both.

29. The memory system of clam 26, wherein the wear logic is configured to:

bundle all sub-sectors of the first sector into a first set of sub-sector bundles;

bundle all sub-sectors of the second sector into a second set of sub-sector bundles; and

swap a position of a first bundle containing the high wear sub-sector with a position of a second bundle containing the minimum sub-sector.