Output Current Monitor Circuit for Switching Regulator

• US 20160141957A1
• Filed: 11/22/2014
• Published: 05/19/2016
• Est. Priority Date: 11/19/2014
• Status: Active Grant

• Current Assignee: Dialog Semiconductors (UK) Limited
• Original Assignee: Dialog Semiconductors (UK) Limited
• Inventors: Ozawa, Seiichi
• Granted Patent: US 9,379,612 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 19/16519 using FET's
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

A circuit and method for providing switching regulation with an improved current monitor comprising a pulse width modulation (PWM) controller configured to provide an output signal voltage, an output stage configured to provide switching comprising a first and second transistor, and first inverter, a sense circuit configured to provide signal sensing from said output stage, a sampling switch circuit configured to provide sample signals from said sense circuit, a differential integrator circuit configured to provide sample signals from said sampling switch circuit, a comparator configured to provide signals from said integrator circuit, a control logic circuit configured to provide signals from said comparator, a current digital-to-analog converter (DAC) configured to provide feedback signal from said control logic circuit, and, a digital filter configured to provide output current information.

Claims

1. A circuit providing switching regulation with an improved current monitor comprising:

an output stage configured to provide switching comprising a first and second transistor;

a sense circuit configured to provide signal sensing from the first transistor in said output stage;

a sampling switch circuit configured to provide sample signals from said sense circuit, wherein the sampling switch circuit is configured to provide a first and second signal to said integrator;

an integrator circuit configured to provide sample signals from said sampling switch circuit;

a comparator configured to provide signals from said integrator circuit; and

a digital-to-analog converter (DAC) configured to provide feedback signal from said comparator.

2. The circuit of claim 1, further comprising:

a pulse width modulation (PWM) controller configured to provide an output signal voltage;

a control logic circuit configured to provide signals from said comparator;

a digital filter configured to provide output current information; and

an inductor coupled to said output stage.

3. The circuit of claim 2, wherein said sense circuit comprises n-channel metal oxide semiconductor (NMOS) transistors electrically coupled to the source and drain of said second transistor.

4. The circuit of claim 2, wherein said sense circuit is configured to provide a first and second signal to said sampling switch circuit.

6. The circuit of claim 1, wherein said integrator circuit comprises a differential amplifier circuit, a first RC integration circuit comprising a first resistor R and first capacitor C, and a second RC integration circuit comprising a second resistor R and second capacitor C, whose capacitor is coupled to the outputs of a differential amplifier circuit and whose inputs are coupled to said sampling switch network.

7. The circuit of claim 6, wherein said comparator is configured to receive a first signal and a second signal from differential integrator circuit.

8. The circuit of claim 2, wherein said digital-to-analog circuit (DAC) is configured to provide a first and second feedback signal to said first and second switch of said sampling switch circuit.

9. The circuit of claim 2, further comprising a feedback loop, a second inverter, and a first and second NMOS feedback network.

10. The circuit of claim 9, configured to provide a feedback signal to said feedback loop, from said sense circuit coupled to said second inverter, coupled to a second NMOS feedback network, and coupled to said comparator, and said control logic.

11. The circuit of claim 1 wherein said control logic circuit further comprises an up/down counter electrically coupled to the comparator output and clock signals, and a DAC control logic inverter coupled to said comparator output.

12. The circuit of claim 11, wherein said digital-to-analog converter (DAC) is coupled to said DAC control logic inverter and is configured to provide an Idacn signal.

13. The circuit of claim 11, wherein said digital-to-analog converter (DAC) is coupled to thermometer decoder wherein said thermometer decoder is electrically coupled to said up/down counter and clock signals and is configured to provide an Idacp signal.

14. The circuit of claim 2, wherein said digital filter is a sinc**2 filter.

15. The circuit of claim 2, wherein said digital filter further comprises a plurality of summers, a plurality of counters, and a 1/M divider.

16. The circuit of claim 1, further comprising a capacitor coupled to said inductor, and said output signal vout.

17. The circuit of claim 1, wherein said switching regulator is a buck converter.

18. The circuit of claim 1, wherein said switching regulator is a boost converter.

23. The circuit of claim 1, wherein the integrator circuit is only ON when the first transistor is ON and wherein the integrator circuit integrates an error between an voltage across the first transistor and an estimated value of said voltage across the first transistor.

5. (canceled)

19. A method of providing an improved current monitor in a switching regulator comprising the steps of:

(a) providing a circuit comprising an output stage, a sense circuit, a sampling switch circuit, wherein said sampling switch circuit is configured to provide a first and second signal to an integrator circuit, said integrator circuit, a comparator, a DAC, and a feedback loop

(b) initiating a NMOS signal to said NMOS of said output stage;

(c) sensing a signal to a sense NMOS circuit providing a first and second, sense signals;

(d) receiving said first and second sense signals to said sampling switch circuit;

(e) integrating said first and second sense signals to said integration circuit;

(f) comparing said integrated signal with said comparator signal;

(g) processing said comparator signal;

(h) feeding a feedback signal to said DAC; and

(i) estimating the average output current.

20. The method of claim 19, further comprising a control logic circuit, further comprise an up/down counter electrically coupled to the comparator output and clock signals, and a DAC control logic inverter coupled to said comparator output.

21. The method of claim 20 wherein said DAC is coupled to said DAC control logic inverter and is configured to provide an Idacn signal.

22. The method of claim 19, further comprising a digital filter wherein said digital filter is a sinc**2 filter.