RESISTIVE MEMORY WITH PROGRAM VERIFY AND ERASE VERIFY CAPABILITY

• US 20160148685A1
• Filed: 11/26/2014
• Published: 05/26/2016
• Est. Priority Date: 11/26/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: ROY, ANIRBAN, SADD, MICHAEL A.
• Granted Patent: US 9,548,116 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
• CPC Class Codes: G11C 2013/0078 Write using current through the cell

Abstract

A resistive non-volatile memory cell is programmed. A programming voltage is applied to a first terminal of the resistive non-volatile memory cell. Sensing, during the applying the programming voltage, determines if the resistive non-volatile memory cell has been programmed. Current is limited through the resistive non-volatile memory cell to a first magnitude. After a predetermined time, if the sensing has not detected that the resistive non-volatile memory cell has been programmed, the current through the resistive non-volatile memory cell is limited to a second magnitude greater than the first magnitude. The resistive non-volatile memory cell is also erased.

Claims

1. A method of programming a resistive non-volatile memory cell, comprising:

applying a programming voltage to a first terminal of the resistive non-volatile memory cell;

sensing, during the applying the programming voltage, if the resistive non-volatile memory cell has been programmed;

limiting current through the resistive non-volatile memory cell to a first magnitude; and

after a predetermined time, if the sensing has not detected that the resistive non-volatile memory cell has been programmed, limiting the current through the resistive non-volatile memory cell to a second magnitude greater than the first magnitude.

2. The method of claim 1, further comprising:

terminating the applying the programming voltage in response to the sensing detecting that, during the applying the programming voltage, the resistive non-volatile memory cell has been programmed.

3. The method of claim 1, wherein the resistive non-volatile memory cell comprises a programmable resistive element and a switching transistor, the programmable resistive element is coupled to a source line, the switching transistor is coupled to a bit line, and the limiting the current is by coupling a current limiter to the bit line.

4. The method of claim 3, further comprising erasing the resistive non-volatile memory cell in an erase mode wherein the erasing comprises applying a voltage limit to the bit line and coupling an impedance between the source line and a supply voltage terminal.

5. The method of claim 4, further comprising sensing, during the applying the voltage limit to the bit line, if the resistive non-volatile memory cell has been erased.

6. The method of claim 5, further comprising, during the erase mode, initially enabling the switching transistor after the applying the voltage limit.

7. The method of claim 6, wherein the initially enabling the transistor after applying the voltage limit prevents the sensing, during the applying the voltage limit to the bit line, from obtaining an erroneous result.

8. The method of claim 5, wherein:

decoupling the impedance from between the source line and a supply voltage terminal in response to the sensing, during the applying the voltage limit to the bit line, making a determination that the resistive non-volatile memory cell has been erased.

9. The method of claim 1, wherein blocking current through the resistive non-volatile memory cell to ground in response to the sensing detecting that, during the applying the programming voltage, the resistive non-volatile memory cell has been programmed.

10. A method of erasing a resistive non-volatile memory cell, comprising:

applying a voltage limit to a first terminal of the resistive non-volatile memory cell;

coupling an impedance between a second terminal of the resistive non-volatile memory cell and a supply voltage terminal;

sensing a state of the memory cell by sensing a voltage on the second terminal of the resistive non-volatile memory cell; and

enabling the resistive non-volatile memory cell after the applying the voltage limit and after the coupling the impedance.

11. The method of claim 10, wherein the resistive non-volatile memory cell comprises a programmable resistive element and a switching transistor, the switching transistor is coupled to a word line, and the enabling the resistive non-volatile memory cell is in response to the word line being enabled.

12. The method of claim 10, further comprising:

decoupling the impedance from between the second terminal of the resistive non-volatile memory cell and the supply voltage terminal in response to the sensing determining that the resistive non-volatile memory cell has been erased while the applying the voltage limit to the first terminal of the resistive non-volatile memory cell is occurring.

13. The method of claim 12, wherein the decoupling uses a flip-flop to retain the decoupling while other resistive non-volatile memory cells may be erased.

14. The method of claim 10, further comprising increasing a magnitude of the voltage limit if the resistive non-volatile memory cell has not been erased after a predetermined time.

15. The method of claim 10 further comprising programming the resistive non-volatile memory cell, wherein the programming comprises:

applying a program signal to the first terminal of the memory cell;

coupling the second terminal of the memory cell to a current limiter set to limit current to a first magnitude;

sensing, during the applying the program signal and the coupling the second terminal, when the resistive non-volatile memory cell has been programmed; and

changing the current limiter to limit the current to a second magnitude greater than the first magnitude.

16. A memory, comprising:

a resistive non-volatile memory cell having an enabling terminal coupled to a word line, a first terminal coupled to a bit line, and a second terminal coupled to a source line;

an auto program verify module coupled to the resistive non-volatile memory cell during a program mode that applies a program signal to the resistive non-volatile memory cell, determines if the resistive non-volatile memory cell has been programmed during application of the program signal, terminates application of the program signal in response to a determination that the resistive non-volatile memory cell has been programmed, provides a current limiter that initially provides a limit to the current through the resistive non-volatile memory cell to a first magnitude and increases the limit to the current through the resistive non-volatile memory cell to a second magnitude during the application of the program signal if the program has not occurred after a predetermined time; and

an auto erase verify module coupled to the resistive non-volatile memory cell during an erase mode that applies a voltage limit to the resistive non-volatile memory cell and determines if the resistive non-volatile memory cell has been erased while the voltage limit is applied.

17. The memory of claim 16, wherein the auto program verify comprises:

a transistor for coupling the program voltage to the source line.

18. The memory of claim 17, wherein the auto program verify module is further characterized by the current limiter comprising a current mirror that is coupled between the bit line and a supply voltage terminal and is decoupled from between the bit line and supply voltage terminal in response to the determination that the resistive non-volatile memory cell has been programmed.

19. The memory circuit of claim 16, wherein the auto erase verify module is further characterized by initially enabling the word line during the erase mode after the voltage limit has been applied.

20. The memory circuit of claim 19, wherein the auto erase verify module is further characterized by further comprising an impedance coupled between the source line and a supply voltage terminal that is decoupled from between the source line and the supply voltage terminal in response to a determination that the resistive non-volatile memory cell has been erased.