PRECISE TIME TAGGING OF EVENTS OVER AN IMPRECESE LINK

• US 20160156458A1
• Filed: 01/25/2016
• Published: 06/02/2016
• Est. Priority Date: 11/04/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Babitch, Daniel, Falk, Henry
• Granted Patent: US 9,929,857 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: H04J 3/0644 External master-clock
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04W 56/001 Synchronization between nodes

Abstract

A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.

Claims

1. A device for precise timing and synchronization of events, comprising:

a first terminal configured to create at least one event tag; and

a second terminal configured to receive and detect the at least one event tag such that when the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the at least one event tag based on a count value of at least one second counter of the second terminal and a count value of at least one first counter of the first terminal.

2. The device according to claim 1, wherein the first terminal includes a packetizer that is configured to create a packetized data stream which includes the at least one event tag.

3. The device according to claim 2, wherein the second terminal includes a depacketizer that is configured to receive the packetized data stream, and wherein the at least one second counter is configured to count clock pulses generated by a first clock of the first terminal at a first clock rate.

4. The device according to claim 1, wherein the second terminal includes at least one serial peripheral interface (SPI) master that outputs an event tag request to at least one SPI slave of the first terminal.

5. The device according to claim 1, wherein the first and second terminals communicate with each other over a wired link interface.

6. The device according to claim 4, wherein the second terminal includes at least one second register that receives an event decode signal from the depacketizer and the count value from the at least one second counter of the second terminal.

7. The device according to claim 6, wherein the second terminal includes at least one software control module that sends a control signal to the SPI master when the count value is received from the at least one second register.

8. The device according to claim 4, wherein the at least one SPI slave sends the event tag request to an event command decoder module that decodes the event tag request and sends a event command decode signal to an event logic module configured to convert the event command decode signal to an event logic signal that is sent to the packetizer of the first terminal and embedded on the packetized data stream event command decode signal.

9. The device according to claim 8, wherein the first terminal further includes at least one first register.

10. The device according to claim 9, wherein the at least one first register receives an event logic signal sent from the event logic module and the count value sent from the at least one first counter of the first terminal, and the at least one first register sends the count value of the first counter to the SPI slave, which sends the first count value of the first counter to the software module of the second terminal.

11. The device according to claim 2, wherein the packetized data stream is created based on a radio frequency (RF) signal received at the first terminal.

12. The device according to claim 3, wherein the at least one first counter is synched to the first clock.

13. The device according to claim 1, wherein the event tag includes a desired bit sequence.

14. A method for precise timing and synchronization of events, comprising:

sending an event tag request from a second terminal to a first terminal;

creating at the first terminal an event tag;

sending the event tag to the second terminal;

detecting the event tag at the second terminal; and

calculating, when the event tag is detected, a time at which the first terminal created the event tag based on a count value of a second counter and a count value of a first counter of the first terminal.

15. The method according to claim 14, further comprising creating a packetized data stream, which includes the event tag, at the first terminal.

16. The method according to claim 14, further comprising counting clock pulses with the second counter of the second terminal, wherein the clock pulses are generated at a first clock rate by a first clock of the first terminal.

17. The method according to claim 14, wherein sending the event tag request further includes sending the event tag request from at least one SPI master of the second terminal to at least one SPI slave of the first terminal.

18. The method according to claim 14, wherein the first and second terminals communicate with each other over a wired link interface.

19. The method according to claim 17, further comprising sending an event decode signal from a depacketizer of the second terminal and the count value from the second counter of the second terminal to at least one second register of the second terminal.

20. The method according to claim 19, further comprising sending a control signal from at least one software control module of the second terminal to the SPI master when the count value is received from the at least one second register.