TRACKING MEMORY ACCESSES WHEN INVALIDATING EFFECTIVE ADDRESS TO REAL ADDRESS TRANSLATIONS

• US 20160179694A1
• Filed: 12/19/2014
• Published: 06/23/2016
• Est. Priority Date: 12/19/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blaner, Bartholomew, Heaslip, Jay G., Lauricella, Kenneth A., Stuecheli, Jeffrey A.
• Granted Patent: US 9,740,629 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/657 Virtual address space management

Abstract

According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

Claims

1-11. -11. (canceled)

12. A processor, comprising:

a bus configured to facilitate the transfer of commands and data messages between multiple processor subsystems coupled to the bus;

a memory;

a memory management unit coupled to the bus, and configured to issue effective address to real address translation invalidation requests;

one or more execution units, configured to issue memory loads and stores using effective addresses;

a plurality of MAEs coupled to the bus;

an ERAT, wherein the ERAT has a plurality of entries, each entry having an indicator;

a tracking array; and

a hardware unit, separate from the one or more execution units, configured to;

receive a first invalidation request;

determine that a first entry in the ERAT corresponds with the first invalidation request;

determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of the plurality of MAEs,

wherein a first MAE can concurrently use a same entry as a second MAE; and

invalidate the first entry in response to determining that the first entry is not being used.

13. The processor in claim 12, wherein the hardware unit is further configured to:

receive a second invalidation request;

determine that a second entry in the ERAT corresponds with the second invalidation request;

determine that a second indicator associated with the second entry indicates that the second entry is being used by at least one MAE; and

stall the second invalidation request while the second entry is being used in response to determining that the second entry is being used.

14. The processor in claim 12, wherein the hardware unit is further configured to:

receive a request to access the memory and performing a first update of a second indicator associated with a second entry in the ERAT corresponding with the request, wherein the second indicator, after the first update, indicates that the second entry is being used in a memory access.

15. The processor in claim 14, wherein the hardware unit is further configured to:

determine that the memory access has finished; and

perform a second update of the second indicator in response to determining that the memory access has finished, wherein the second indicator, after the second update, indicates that the entry is not being used in the memory access.

16. The processor in claim 12, wherein the indicator associated with each ERAT entry is a counter.

17. The processor in claim 12, wherein the indicator associated with each ERAT entry is a single bit in a bit-field.

18. The processor in claim 12, wherein a tracking array tracks entries each one of the plurality of MAEs uses.

19. The processor in claim 18, wherein the tracking array has a plurality of elements, each element associated with one of the plurality of MAEs.