Multi-level Inverter with Flying Capacitor Topology

• US 20160181950A1
• Filed: 02/26/2016
• Published: 06/23/2016
• Est. Priority Date: 03/26/2014
• Status: Active Grant

• Current Assignee: Solaredge Technologies Incorporated
• Original Assignee: Solaredge Technologies Incorporated
• Inventors: Yoscovich, Ilan, Glovinsky, Tzachi, Sella, Guy, Galin, Yoav
• Granted Patent: US 10,404,154 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02M 1/0054 Transistor switching losses periodically suspending operation of switching converter in low power mode H02M1/0035
• CPC Class Codes: H02M 1/0095 Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/126 using passive filters
• CPC Class Codes: H02M 1/143 using compensating arrangements for reducing noise from the supply in transmission systems H04B15/005
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/4833 Capacitor voltage balancing
• CPC Class Codes: H02M 7/4835 comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
• CPC Class Codes: H02M 7/4837 Flying capacitor converters
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters

Abstract

A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

Claims

1. A method comprising:

switching at different times each of a plurality of low voltage MOSFET transistors connected in series in a first bank of a multi-level inverter comprising at least one bank of MOSFET transistors.

2. The method of claim 1, wherein switching of the first bank includes switching at different times more than two low voltage MOSFET transistors.

3. The method of claim 1, wherein switching at different times each of the plurality of low voltage MOSFET transistors comprises:

turning on any one low voltage MOSFET transistor in the bank with a time delay between turning off the one low voltage MOSFET transistor and turning on another low voltage MOSFET transistor in the first bank.

4. The method of claim 1, wherein the switching occurs at a cycle time of about 50 kHz or about 200 kHz for each transistor.

5. The method of claim 1, further comprising

switching at the different times each of a second plurality of low voltage MOSFET transistors connected in a second bank of the multi-level inverter, each of the second plurality of low voltage MOSFET transistors being switched at a common time as a respective one of the plurality of low voltage MOSFET transistors.

6. The method of claim 5, further comprising:

adjusting switching duty cycles of one of the second plurality of low voltage MOSFET transistors and the respective one of the plurality of low voltage MOSFET transistors switched at the common time to different values such that voltage across one of a plurality of switching capacitors in the multi-level inverter is compensated in response to switch mismatches.

7. The method of claim 1, further comprising

switching at the different times each of a second plurality of low voltage MOSFET transistors connected in a second bank of the multi-level inverter, each of the second plurality of low voltage MOSFET transistors being switched at a common time and in an opposite state as a respective one of the plurality of low voltage MOSFET transistors.

8. The method of claim 1, further comprising:

switching the first bank, a second bank, a third bank, and a fourth bank of low voltage MOSFET transistors in the multi-level inverter, the first bank being connected in series with the second bank, the third bank being connected in series with the fourth bank, and the first and the second banks being connected to a first phase of an output of the multi-level inverter, and the third and the fourth banks being connected in a second phase of the output of the multi-level inverter.

9. The method of claim 8, further comprising:

providing a first control signal to switch one of the MOSFET transistors of the first bank and one of the MOSFET transistors of the fourth bank; and

providing an inverted first control signal comprising an inverted version of the first control signal to switch one of the MOSFET transistors of the second bank and one of the MOSFET transistors of the third bank.

10. The method of claim 9, further comprising,

connecting a resistor across each of the low voltage MOSFET transistors such that switching capacitors in the multi-level inverter are pre-charged to respective voltages.

11. The method of claim 1, the different times being separated by 1/N of a switching frequency of the transistors and N being a number of transistors in the plurality of low voltage MOSFET transistors.

12. The method of claim 1, further comprising:

changing a switching duty cycle of each of the plurality of the low voltage MOSFET transistors such that voltage at an output of the multi-level inverter is varied between two predetermined values.

13. A multi-level inverter comprising:

a first bank and a second bank of series connected switches, the first bank and the second bank connected in series between an input voltage terminal and a reference voltage terminal;

a plurality of capacitors, each of the capacitors having a first capacitor terminal connected between two adjacent ones of switches of the first bank and a second capacitor terminal connected between two adjacent ones of the switches of the second bank; and

a controller configured to control a plurality of switch pairs, each pair being switched at different times during a switching cycle, and each switch pair comprising a switch in the first bank and a respective switch in the second bank.

14. The multi-level inverter of claim 13, further comprising:

a third bank and a fourth bank of series connected switches, the third bank and the fourth bank connected in series between the input voltage terminal and the reference voltage terminal;

a first phase output terminal and a second phase output terminal;

a first inductor connected between the first phase output terminal and a first node connecting the first bank to the second bank; and

a second inductor connected between the second phase output terminal and a second node connecting the third bank to the fourth bank.

15. The multi-level inverter of claim 14, wherein the controller is configured to:

control a plurality of second switch pairs, each of the second switch pairs comprising a switch in the third bank and a respective switch in the fourth bank, each of the second switch pairs being switched simultaneously with a respective one of the switch pairs.

16. The multi-level inverter of claim 13, further comprising

an inductor and a storage capacitor connected in series between a node connecting the first bank to the second bank and either the input voltage terminal and the reference voltage terminal.

17. The multi-level inverter of claim 13, wherein each of the series connected switches of the first bank and the second bank comprise a low voltage MOSFET transistor.

18. The multi-level inverter of claim 17, wherein each of series connected switches of the first bank and the second bank comprise a switched resistor bypassing the low voltage MOSFET transistor.

19. The multi-level inverter of claim 17, wherein the low voltage MOSFET transistors operate at 80V or at 150V.

20. The multi-level inverter of claim 13, wherein the controller is configured to switch each of the switches at a cycle frequency of about 50 kHz or about 200 kHz.