ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY APPARATUS

• US 20160197100A1
• Filed: 04/17/2015
• Published: 07/07/2016
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Song, Ruitao, Li, Chun, Wang, Yanming, Wu, Tao, Sun, Hongwei
• Granted Patent: US 9,905,591 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136272 Auxiliary lines
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Abstract

An array substrate and a manufacturing method thereof, a display apparatus are disclosed. The manufacturing method of the array substrate includes a forming a conduction layer (20) for electrically connecting two adjacent pixel electrodes (104) upon forming of the pixel electrodes (104). The method further includes forming a photoresist layer (30) on a surface of a substrate with the conduction layer (20) formed thereon; through one exposure and development process, forming a first photoresist removed region (A) and a photoresist retained region (B). The first photoresist removed region (A) corresponds to a location of the conduction layer (20); the conduction layer (20) in the first photoresist removed region (A) is etched, to form a separating region (106) configured for avoiding electrical connection of pixel electrodes (104) of two adjacent pixel units; and within the separating region (106), a metal line that is non-electrically connected to adjacent two pixel electrodes (104) is formed. With the array substrate and manufacturing method thereof, damage to excessive thin film layers in the array substrate in the course of reducing bright dot defect can be avoided.

Claims

1. A method for manufacturing an array substrate, comprising a process for forming a plurality of pixel electrodes arranged in the form of a matrix, with a conduction layer for electrically connecting two adjacent pixel electrodes being formed upon formation of the pixel electrodes,

the method further comprising:

forming a photoresist layer on a surface of a substrate with the conduction layer formed thereon;

through one exposure and development process, forming a first photoresist removed region that corresponds to a location of the conduction layer and a photoresist retained region that corresponds to other region on the surface of the substrate with the conduction layer formed thereon;

etching the conduction layer in the first photoresist removed region, to form a separating region for avoiding electrical connection of two adjacent pixel electrodes; and

stripping the photoresist layer in the photoresist retained region;

forming a metal layer on the surface of the substrate with above structures formed thereon;

through one patterning process and within the separating region, forming a metal line that is non-electrically connected to two adjacent pixel electrodes.

2. The method according to claim 1, wherein the method comprises, after the forming of the first photoresist removed region and the photoresist retained region through one exposure and development process, and before the etching of the conduction layer in the first photoresist removed region,

the first photoresist removed region corresponds to the separating region to be formed, and the photoresist retained region corresponds to other region on the surface of the substrate with the conduction layer formed thereon.

3. The method according to claim 1, wherein the method comprises, after the forming of the first photoresist removed region and the photoresist retained region through one exposure and development process, and before the etching of the conduction layer in the first photoresist removed region,

the first photoresist removed region corresponds to a recess to be formed, the photoresist retained region corresponds to other region on the surface of the substrate with the conduction layer formed thereon;

the separating region to be formed includes two recesses as stated and an insulating section located between the two recesses.

4. The method according to claim 1, wherein, the metal layer comprises a gate metal layer or a source/drain metal layer.

5. The method according to claim 1, wherein, in the event that the array substrate comprises a gate insulating layer, upon etching the conduction layer in the first photoresist removed region, a part of the gate insulating layer is etched.

6. The method according to claim 1 the method further comprising, during the forming of the first photoresist removed region and the photoresist retained region through one exposure and development process,

forming a second photoresist removed region, which corresponds to a lead via hole to be formed;

etching the gate insulating layer in the second photoresist removed region, to form the lead via hole.

7. The method according to claim 1, the method further comprising, after the forming of the metal line at the location corresponding to the separating region through the patterning process,

forming a passivation layer on the surface of the substrate with above structures formed thereon;

forming a common electrode layer on a surface of the passivation layer.

8. The method according to claim 7, wherein, the width range of the separating region is 12 μ

m to 20 μ

m.

15. The method according to claim 1, wherein the first photoresist removed region corresponds to the separating region to be formed, and the photoresist retained region corresponds to other region on the surface of the substrate with the conduction layer formed thereon.

16. The method according to claim 1, wherein the first photoresist removed region corresponds to a recess to be formed, the photoresist retained region corresponds to other region on the surface of the substrate with the conduction layer formed thereon;

the separating region to be formed includes two recesses as stated and an insulating section located between the two recesses.

17. The method according to claim 2, the method further comprising, after the forming of the metal line at the location corresponding to the separating region through the patterning process,

forming a passivation layer on the surface of the substrate with above structures formed thereon;

forming a common electrode layer on a surface of the passivation layer.

18. The method according to claim 3, the method further comprising, after the forming of the metal line at the location corresponding to the separating region through the patterning process,

forming a passivation layer on the surface of the substrate with above structures formed thereon;

forming a common electrode layer on a surface of the passivation layer.

19. The method according to claim 5, the method further comprising, after the forming of the metal line at the location corresponding to the separating region through the patterning process,

forming a passivation layer on the surface of the substrate with above structures formed thereon;

forming a common electrode layer on a surface of the passivation layer.

9. An array substrate, comprising a plurality of pixel electrodes arranged in the form of a matrix, a separating region configured for avoiding electrical connection of two adjacent pixel electrodes, and a metal line that is situated within the separating region and is non-electrically connected to the two adjacent pixel electrode.

10. The array substrate according to claim 9, wherein, only the metal line is provided within the separating region.

11. The array substrate according to claim 9, wherein, the separating region includes two recesses, and an insulating section located between the two recesses, and the metal line is located on a surface of the insulating section.

12. A display apparatus, comprising the array substrate according to claim 9.

13. The display apparatus according to claim 12, wherein, only the metal line is provided within the separating region.

14. The display apparatus according to claim 12, wherein, the separating region includes two recesses, and an insulating section located between the two recesses, and the metal line is located on a surface of the insulating section.