VERTICAL POWER TRANSISTOR DEVICE

• US 20160211360A1
• Filed: 03/31/2016
• Published: 07/21/2016
• Est. Priority Date: 08/08/2013
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Pala, Vipindas, Agarwal, Anant Kumar, Cheng, Lin, Lichtenwalner, Daniel Jenner, Palmour, John Williams
• Granted Patent: US 9,741,842 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

Claims

1. (canceled)

2. A transistor device comprising:

a substrate;

a drift layer on the substrate;

a spreading layer on the drift layer; and

a gate, a drain, and a source;

wherein a channel width of the transistor device is less than 3 microns, an on-state resistance of the transistor device is less than 2.5 mΩ

/cm², and a blocking voltage of the transistor device is greater than 600 volts.

3. The transistor device of claim 2 wherein the on-state resistance of the transistor device is less than 2.0 mΩ

/cm².

4. The transistor device of claim 3 wherein the blocking voltage of the transistor device is greater than 1200 volts.

5. The transistor device of claim 2 wherein the blocking voltage of the transistor device is greater than 1200 volts.

6. The transistor device of claim 2 wherein the transistor device comprises silicon carbide.

7. The transistor device of claim 2 wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).

8. The transistor device of claim 2 wherein a ratio of a doping concentration at a first surface of the spreading layer adjacent to the drift layer and a doping concentration at a second surface of the spreading layer opposite the first surface is between 1:

2 and 1;

8.

9. The transistor device of claim 8 wherein a thickness of the spreading layer is between 1.0 microns and 2.5 microns.

10. The transistor device of claim 8 wherein the doping concentration at the first surface of the spreading layer is 5×

10¹⁶ cm<sup>−

3</sup> and the doping concentration at the second surface of the spreading layer is 2×

10¹⁷ cm<sup>−

3</sup>.

11. A transistor device comprising:

a substrate;

a drift layer on the substrate;

a spreading layer on the drift layer, the spreading layer comprising a first surface adjacent to the drift layer and a second surface opposite the first surface, wherein a difference between a doping concentration at the first surface and a doping concentration at the second surface is greater than 100 cm<sup>−

3</sup>; and

a gate, a drain, and a source.

12. The transistor device of claim 11 wherein a ratio of a doping concentration at the first surface to a doping concentration at the second surface is between 1:

2 and 1;

8.

13. The transistor device of claim 12 wherein the ratio of the doping concentration at the first surface of the spreading layer to the doping concentration at the second surface of the spreading layer is between 1:

4 and 1;

8.

14. The transistor device of claim 13 wherein a thickness of the spreading layer is between 1.0 microns and 2.5 microns.

15. The transistor device of claim 12 wherein the ratio of the doping concentration at the first surface of the spreading layer to the doping concentration at the second surface of the spreading layer is between 1:

6 and 1;

8.

16. The transistor device of claim 15 wherein a thickness of the spreading layer is between 1.0 microns and 2.5 microns.

17. The transistor device of claim 12 wherein the transistor device comprises silicon carbide.

18. The transistor device of claim 12 wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).

19. The transistor device of claim 12 wherein a thickness of the spreading layer is between 1.0 microns and 2.5 microns.

20. The transistor device of claim 12 wherein the doping concentration at the first surface of the spreading layer is 5×

10¹⁶ cm<sup>−

3</sup> and the doping concentration at the second surface of the spreading layer is 2×

10¹⁷ cm<sup>−

3</sup>.

21. The transistor device of claim 12 wherein the spreading layer comprises multiple epitaxial layers each with a different doping concentration such that the doping concentration between the first surface and the second surface is graded.

22. The transistor device of claim 21 wherein a channel width of the transistor device is less than 3 microns, an on-state resistance of the transistor device is less than 2.5 mΩ

/cm², and a blocking voltage of the transistor device is greater than 600 volts.