Current Output Architecture for an Implantable Stimulator Device

• US 20160213914A1
• Filed: 04/06/2016
• Published: 07/28/2016
• Est. Priority Date: 07/08/2005
• Status: Active Grant

• Current Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Original Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Inventors: He, Yuping, Peterson, David K.L.
• Granted Patent: US 9,931,502 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: A61N 1/0551 Spinal or peripheral nerve electrodes
• CPC Class Codes: A61N 1/36185 Selection of the electrode configuration

Abstract

Disclosed herein are current output architectures for implantable stimulator devices. Current source and sink circuitry is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking an amount of current to or from any one of the electrodes of the device. The current source circuitry is distinct from the current sink circuitry, and the two share no common circuit nodes prior to connection to the electrodes. In other words, the current source circuitry and the current sink circuitry do not share a common node other than the electrodes. Each stage is preferably formed of a current mirror for receiving a reference current and outputting a scaled version of current to that stage'"'"'s switch bank. The scalar at each stage can be set by wiring a desired number of output transistors in parallel.

Claims

1. An implantable stimulator device, comprising:

a plurality of N electrode nodes implantable adjacent to tissue to be stimulated;

a plurality of L first stages, each first stage comprising;

a first current source configured to provide a first current of a pre-set non-adjustable magnitude, and

a plurality of N first switches each controllable to source the first current to one of the plurality of N electrode nodes.

2. The device of claim 1, wherein the first current sources are not individually selectable.

3. The device of claim 1, wherein the first current sources are coupled to a first power supply.

4. The device of claim 1, wherein the first current sources are configured to respectively convert a reference current into the first currents.

5. The device of claim 4, wherein the first currents comprise scalars of the reference current.

6. The device of claim 5, wherein the first currents are equal in magnitude to the reference current.

7. The device of claim 1, wherein the first currents are of equal magnitude in the first stages.

8. The device of claim 1, wherein the first currents are not of equal magnitude in the first stages.

9. The device of claim 8, wherein the magnitude of the first currents varies linearly across at least some of the first stages.

10. The device of claim 8, wherein the magnitude of the first currents varies exponentially across at least some of the first stages.

11. The device of claim 1, wherein the first current sources comprise first current mirrors.

12. The device of claim 11, wherein a scalar between a reference current and the first current in each stage is set by a number of parallel output transistors in each first current mirror.

13. The device of claim 1, wherein N does not equal L.

14. The device of claim 1, wherein L is greater than N.

15. The device of claim 1, wherein N equals L.

16. The device of claim 1, further comprising:

a plurality of L second stages, each second stage comprising;

a second current source configured to provide a second current of a pre-set non-adjustable magnitude, and

a plurality of N second switches each controllable to sink the second current from one of the plurality of N electrode nodes.

17. The device of claim 16, wherein the second current sources are not individually selectable.

18. The device of claim 16, wherein the second current sources are coupled to a second power supply.

19. The device of claim 16, wherein the second current sources are configured to respectively convert a reference current into the second currents.

20. The device of claim 19, wherein the second currents comprise scalars of the reference current.

21. The device of claim 20, wherein the second currents are equal in magnitude to the reference current.

22. The device of claim 16, wherein the second currents are of equal magnitude in the second stages.

23. The device of claim 16, wherein the second currents are not of equal magnitude in the second stages.

24. The device of claim 16, wherein the second current sources comprise second current mirrors.

25. The device of claim 24, wherein a scalar between a reference current and the second current in each stage is set by a number of parallel output transistors in each second current mirror.