METHOD FOR OPERATING SEMICONDUCTOR DEVICE

• US 20160217830A1
• Filed: 01/15/2016
• Published: 07/28/2016
• Est. Priority Date: 01/23/2015
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: TSUBUKU, Masashi, FUJITA, Masashi
• Granted Patent: US 9,633,710 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.

Claims

1. A method for operating a semiconductor device comprising a capacitor and a switching element,

wherein the capacitor comprises a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode, and

wherein the switching element comprises a first terminal and a second terminal, the first terminal being electrically connected to the first electrode,

the method comprising steps of:

turning on the switching element in a first period;

turning off the switching element in a second period longer than or equal to 1 ns and shorter than or equal to 500 μ

s; and

turning on the switching element in a third period,

wherein the first period, the second period, and the third period are continuous in this order.

2. The method for operating the semiconductor device, according to claim 1,

wherein the first period and the third period are each longer than or equal to 50 ps and shorter than or equal to 1 ms.

3. The method for operating the semiconductor device, according to claim 1,

wherein the switching element is included in a memory element, and

wherein no reading operation of the memory element is performed in the second period.

4. The method for operating the semiconductor device, according to claim 1,

wherein the dielectric comprises oxygen and at least one element selected from silicon, aluminum, and hafnium.

5. The method for operating the semiconductor device, according to claim 1,

wherein the switching element comprises an oxide semiconductor.

6. The method for operating the semiconductor device, according to claim 1,

wherein the switching element is a transistor comprising an oxide semiconductor.

7. A method for operating a semiconductor device comprising a capacitor and a transistor,

wherein the capacitor comprises a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode, and

wherein the transistor comprises a gate electrode, a third electrode, and a fourth electrode, the third electrode being electrically connected to the first electrode,

the method comprising steps of:

applying a first potential to the gate electrode and a second potential to the second electrode in a first period;

applying a third potential to the gate electrode and a fourth potential to the second electrode in a second period, the second period being longer than or equal to 1 ns and shorter than or equal to 500 μ

s; and

applying a fifth potential to the gate electrode and a sixth potential to the second electrode in a third period,

wherein the first period, the second period, and the third period are continuous in this order,

wherein a difference between the first potential and the second potential is larger than a difference between the third potential and the fourth potential, and

wherein a difference between the fifth potential and the sixth potential is larger than the difference between the third potential and the fourth potential.

8. The method for operating the semiconductor device, according to claim 7, wherein a difference between the second potential and the fourth potential is 0.2 V or less.

9. The method for operating the semiconductor device, according to claim 7, wherein the first period and the third period are each longer than or equal to 50 ps and shorter than or equal to 1 ms.

10. The method for operating the semiconductor device, according to claim 7,

wherein the transistor is included in a memory element, and

wherein no reading operation of the memory element is performed in the second period.

11. The method for operating the semiconductor device, according to claim 7,

wherein the dielectric comprises oxygen and silicon.

12. The method for operating the semiconductor device, according to claim 7,

wherein the transistor comprises an oxide semiconductor.

13. The method for operating the semiconductor device, according to claim 7,

wherein the semiconductor device comprises a second transistor, and

wherein the first electrode is electrically connected to a gate electrode of the second transistor.

14. The method for operating the semiconductor device, according to claim 7,

wherein the transistor is in an on state in each of the first period and the third period, and

wherein the transistor is in an off state in the second period.

15. A method for operating a semiconductor device comprising a first memory element and a second memory element,

wherein each of the first memory element and the second memory element comprises a capacitor and a switching element,

wherein the capacitor comprises a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode, and

wherein the switching element comprises a first terminal and a second terminal, the first terminal being electrically connected to the first electrode,

the method comprising steps of:

turning on the switching element of the first memory element in a first period;

turning off the switching element of the first memory element in a second period;

turning on the switching element of the first memory element in a third period;

turning on the switching element of the second memory element in a fourth period;

turning off the switching element of the second memory element in a fifth period; and

turning on the switching element of the second memory element in a sixth period,

wherein the first period, the second period, and the third period are continuous in this order, and

wherein the fourth period, the fifth period, and the sixth period are continuous in this order.

16. The method for operating the semiconductor device, according to claim 15,

wherein the first period, the third period, the fourth period, and the sixth period are each longer than or equal to 50 ps and shorter than or equal to 1 ms, and

wherein the second period and the fifth period are each longer than or equal to 50 ps and shorter than or equal to 100 ms.

17. The method for operating the semiconductor device, according to claim 15,

wherein the switching element is included in a memory element, and

wherein no reading operation of the memory element is performed in the second period and the fifth period.

18. The method for operating the semiconductor device, according to claim 15,

wherein the dielectric comprises oxygen and at least one element selected from silicon, aluminum, and hafnium.

19. The method for operating the semiconductor device, according to claim 15,

wherein the switching element comprises an oxide semiconductor.

20. The method for operating the semiconductor device, according to claim 15,

wherein the switching element is a transistor comprising an oxide semiconductor.

21. A method for operating a semiconductor device comprising a first memory element and a second memory element,

wherein each of the first memory element and the second memory element comprises a capacitor and a transistor,

wherein the capacitor comprises a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode, and

wherein the transistor comprises a gate electrode, a third electrode, and a fourth electrode, the third electrode being electrically connected to the first electrode,

the method comprising steps of:

applying a first potential to the gate electrode of the first memory element and a second potential to the second electrode of the first memory element in a first period;

applying a third potential to the gate electrode of the first memory element and a fourth potential to the second electrode of the first memory element in a second period;

applying a fifth potential to the gate electrode of the first memory element and a sixth potential to the second electrode of the first memory element in a third period;

applying the first potential to the gate electrode of the second memory element and the second potential to the second electrode of the second memory element in a fourth period;

applying the third potential to the gate electrode of the second memory element and the fourth potential to the second electrode of the second memory element in a fifth period;

applying the fifth potential to the gate electrode of the second memory element and the sixth potential to the second electrode of the second memory element in a sixth period,

wherein the first period, the second period, and the third period are continuous in this order,

wherein the fourth period, the fifth period, and the sixth period are continuous in this order,

wherein a difference between the first potential and the second potential is larger than a difference between the third potential and the fourth potential, and

wherein a difference between the fifth potential and the sixth potential is larger than the difference between the third potential and the fourth potential.

22. The method for operating the semiconductor device, according to claim 21, wherein a difference between the second potential and the fourth potential is 0.2 V or less.

23. The method for operating the semiconductor device, according to claim 21,

wherein the first period, the third period, the fourth period, and the sixth period are each longer than or equal to 50 ps and shorter than or equal to 1 ms, and

wherein the second period and the fifth period are each longer than or equal to 50 ps and shorter than or equal to 100 ms.

24. The method for operating the semiconductor device, according to claim 21,

wherein the transistor is included in a memory element, and

wherein no reading operation of the memory element is performed in the second period.

25. The method for operating the semiconductor device, according to claim 21,

wherein the dielectric comprises oxygen and silicon.

26. The method for operating the semiconductor device, according to claim 21,

wherein the transistor comprises an oxide semiconductor.

27. The method for operating the semiconductor device, according to claim 21,

wherein the semiconductor device comprises a second transistor, and

wherein the first electrode is electrically connected to a gate electrode of the second transistor.

28. The method for operating the semiconductor device, according to claim 21,

wherein the transistor is in an on state in each of the first period, the third period, the fourth period, and the sixth period, and

wherein the transistor is in an off state in each of the second period and the fifth period.