ABNORMAL CLOCK RATE DETECTION IN IMAGING SENSOR ARRAYS

• US 20160224055A1
• Filed: 12/07/2015
• Published: 08/04/2016
• Est. Priority Date: 04/23/2010
• Status: Active Grant

• Current Assignee: Teledyne FLIR LLC (Teledyne Technologies Incorporated)
• Original Assignee: FLIR Systems, Inc. (Teledyne Technologies Incorporated)
• Inventors: Simolon, Brian, Kurth, Eric A., Goodland, Jim, Nussmeier, Mark, Hogasten, Nicholas, Hoelter, Theodore R., Strandemar, Katrin, Boulanger, Pierre, Sharp, Barbara, Aziz, Naseem Y.
• Granted Patent: US 9,948,878 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 23/00 Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 11/0703 Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: H04N 23/57 Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20

Abstract

Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select a current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

Claims

1. A device comprising:

a counter configured to receive a clock signal and adjust a count value in response to the clock signal;

a ramp generator configured to generate a ramp signal having a slope independent of the clock signal;

a comparator configured to receive a reference signal via a first input and the ramp signal via a second input, and select a current count value of the counter in response to the reference signal and the ramp signal; and

a processor configured to determine, based on the current count value, if a frequency of the clock signal is within a specified range.

2. The device of claim 1, wherein the reference signal and the ramp signal exhibit similar variations over temperature such that the current count value selected by the comparator is substantially stable over temperature.

3. The device of claim 2, further comprising:

a reference signal generator configured to generate the reference signal that is independent of the clock signal; and

a matched pair of first and second analog components that are configured to pass or generate analog signals that exhibit similar variations over temperature,

wherein the first analog component is provided in a signal path between the reference signal generator and the first input of the comparator, and

wherein the second analog component is provided in a signal path between the ramp generator and the second input of the comparator.

4. The device of claim 3, wherein the matched pair comprises a matched pair of first and second buffers.

5. The device of claim 4, wherein the first and the second buffers are level shift buffers.

6. A method comprising:

adjusting a count value in response to a clock signal;

generating a ramp signal having a slope independent of the clock signal;

selecting a current value of the count value in response to the reference signal and the ramp signal; and

determining, based on the current count value, if a frequency of the clock signal is within a specified range.

7. The method of claim 6, wherein the reference signal and the ramp signal exhibit similar variations over temperature such that the selecting of the current count value is substantially stable over temperature.

8. The method of claim 7, further comprising:

passing or adjusting the reference signal by a first analog component prior to the selecting; and

passing or adjusting the ramp signal by a second analog component prior to the selecting,

wherein the first and the second analog components are provided as a matched pair configured to exhibit similar temperature-dependent variations in the passed or adjusted signals.

9. The method of claim 8, wherein:

the matched pair comprises a matched pair of first and second buffers;

the passing or adjusting of the reference signal comprises buffering the reference signal by the first buffer; and

the passing or adjusting of the ramp signal comprises buffering the ramp signal by the second buffer.

10. The method of claim 9, wherein:

the first and the second buffers are level shift buffers;

the buffering of the reference signal comprises shifting the reference signal by a predetermined level; and

the buffering of the ramp signal comprises shifting the ramp signal by the predetermine level.