ENHANCED CHANNEL MOBILITY THREE-DIMENSIONAL MEMORY STRUCTURE AND METHOD OF MAKING THEREOF

• US 20160233227A1
• Filed: 02/11/2015
• Published: 08/11/2016
• Est. Priority Date: 02/11/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: ZHANG, Yanli, MAKALA, Raghuveer S., ALSMEIER, Johann
• Granted Patent: US 9,627,395 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein. The contiguous semiconductor material portion includes an amorphous or polycrystalline semiconductor material. A metallic material portion is provided at a bottom surface of the semiconductor channel, at a top surface of the semiconductor channel, or on portions of an outer sidewall surface of the semiconductor channel. An anneal is performed to induce diffusion of a metal from the metallic material portion through the semiconductor channel, thereby inducing conversion of the amorphous or polycrystalline semiconductor material into a crystalline semiconductor material. The crystalline semiconductor material has a relatively large grain size due to the catalytic crystallization process, and can provide enhanced charge carrier mobility.

Claims

1. A method of manufacturing a monolithic three-dimensional memory device, comprising:

forming a stack including an alternating plurality of first material layers and second material layers over a substrate;

forming an opening that vertically extends through the stack;

forming a semiconductor channel comprising an amorphous or polycrystalline semiconductor material over a sidewall of the opening, wherein the semiconductor channel extends through the stack; and

diffusing a metallic material through at least a portion of the semiconductor channel, wherein the metallic material induces crystallization of the amorphous or polycrystalline semiconductor material in the semiconductor channel into a crystalline semiconductor material portion.

2. The method of claim 1, further comprising:

forming a metallic material layer comprising the metallic material on a surface of the semiconductor channel; and

annealing the semiconductor channel comprising the amorphous or polycrystalline semiconductor material and the metallic material layer in an anneal process, wherein the metallic material diffuses through the semiconductor channel during the anneal process to crystallize the amorphous or polycrystalline semiconductor material.

3. The method of claim 2, wherein the metallic material diffuses downward from a top portion of the semiconductor channel to a bottommost portion of the semiconductor channel.

4. The method of claim 3, wherein a metal semiconductor alloy region is formed at a bottom region of the semiconductor channel, the metal semiconductor alloy region comprises an alloy of the metallic material and the amorphous or polycrystalline semiconductor material.

5. The method of claim 2, further comprising forming a memory film on the sidewall of the opening, wherein the semiconductor channel is formed on the memory film.

6. The method of claim 5, wherein the semiconductor channel is electrically isolated from the substrate by a horizontal portion of the memory film after formation of the crystalline semiconductor material portion.

7. The method of claim 1, further comprising:

forming a memory film on the sidewall of the opening, wherein the semiconductor channel is formed on the memory film; and

forming an integrated via and layer structure that contacts a region of the crystalline semiconductor material portion and extending through the stack along a direction parallel to a top surface of the substrate.

8. The method of claim 7, further comprising forming a plurality of control gate electrodes around the memory film at each level that corresponds to the second material layers.

9. The method of claim 8, wherein the region of the crystalline semiconductor material portion is located underneath the plurality of control gate electrodes.

10. The method of claim 7, further comprising:

forming a contact via trench through the stack;

forming a lateral cavity that extends between the contact via trench and a portion of the memory film; and

physically exposing a surface of the semiconductor channel by removing the portion of the memory film, wherein the integrated via and layer structure is formed by depositing at least one conductive material on the physically exposed surface of a region of the crystalline semiconductor material portion.

11. The method of claim 10, wherein the region of the crystalline semiconductor material portion is a source region that is formed by introducing electrical dopants through the surface of the semiconductor channel.

12. The method of claim 1, further comprising:

forming a metallic material portion comprising the metallic material over the substrate, wherein the semiconductor channel is formed on the metallic material portion; and

annealing the semiconductor channel comprising the amorphous or polycrystalline semiconductor material and the metallic material layer in an anneal process, wherein the metallic material diffuses through the semiconductor channel during the anneal process to induce crystallization of the amorphous or polycrystalline semiconductor material in the semiconductor channel.

13. The method of claim 12, wherein the metallic material diffuses upward to an inner sidewall of the semiconductor channel.

14. The method of claim 12, wherein:

the anneal process induces formation of a metal semiconductor alloy region over a top portion of the semiconductor channel; and

the metal semiconductor alloy region comprises an alloy of the metallic material and the amorphous or polycrystalline semiconductor material.

15. The method of claim 14, further comprising removing the metal semiconductor alloy region.

16. The method of claim 12, further comprising forming a memory film on the sidewall of the opening, wherein the semiconductor channel is formed on the memory film.

17. The method of claim 16, wherein the semiconductor channel is formed by:

forming a first semiconductor channel layer on an inner sidewall of the memory film;

extending the opening through bottom portions of the first semiconductor channel layer and the memory film and to a top surface of the metallic material portion; and

forming a second semiconductor channel layer on the first semiconductor channel layer and the metallic material portion, wherein the first and second semiconductor channel layers collectively constitute the semiconductor channel.

18. The method of claim 16, wherein:

the substrate comprises a semiconductor material portion;

the metallic material portion is formed on the semiconductor material portion; and

the crystalline semiconductor material portion of the semiconductor channel contacts the semiconductor material portion after the anneal process.

19. The method of claim 1, further comprising forming backside recesses by removing the second material layers selective to the first material layers, wherein a portion of the outer sidewall of the semiconductor channel comprising the amorphous or polycrystalline semiconductor material is physically exposed in each backside recess.

20. The method of claim 19, further comprising:

forming a metallic material layer comprising the metallic material in the backside recesses and on portions of an outer sidewall of the semiconductor channel; and

annealing the semiconductor channel comprising the amorphous or polycrystalline semiconductor material and the metallic material layer in an anneal process, wherein the metallic material diffuses through the semiconductor channel during the anneal process to induce crystallization of the amorphous or polycrystalline semiconductor material in the semiconductor channel.

21. The method of claim 20, wherein the metallic material diffuses laterally and inward to an inner surface of the semiconductor channel.

22. The method of claim 21, wherein at least one metal semiconductor alloy region is formed at an inner sidewall of the semiconductor channel, the metal semiconductor alloy region comprises an alloy of the metallic material and the amorphous or polycrystalline semiconductor material.

23. The method of claim 22, further comprising removing the at least one metal semiconductor alloy region from the inner sidewall of the semiconductor channel.

24. The method of claim 20, further comprising:

removing remaining portions of the metallic material layer from the backside recesses after the anneal process; and

forming a memory film on each portion of an outer sidewall of the semiconductor channel through the backside recesses.

25. The method of claim 24, wherein forming the memory film comprises:

forming a tunneling dielectric on each physically exposed surface of the semiconductor channel within the backside recesses;

forming a plurality of floating gate electrodes on the tunneling dielectric; and

forming a blocking dielectric on the plurality of floating gate electrodes.

26. The method of claim 20, wherein the semiconductor channel is formed directly on a sidewall of the opening prior to formation of the backside recesses.

27. The method of claim 20, further comprising forming a plurality of control gate electrodes around the opening within portions of the backside recesses at each level that corresponds to the second material layers.

28. The method of claim 1, wherein:

the semiconductor channel comprises a material selected from amorphous silicon, polycrystalline silicon, an amorphous silicon-germanium alloy, and an polycrystalline silicon-germanium alloy; and

the metallic material comprises a material selected from a transition metal element, a combination of two or more transition metal elements, an oxide thereof, and a nitride thereof.

29. The method of claim 1, wherein:

the three-dimensional memory device comprises a vertical NAND device formed in a device region; and

forming electrically conductive layers at levels corresponding to the second material layers, wherein the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device.

30. The method of claim 29, wherein:

the device region comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;

the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including a plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

31. A three-dimensional memory device, comprising:

a stack including an alternating plurality of insulator layers and electrically conductive layers and located over a top surface of a substrate;

an opening extending through the stack;

a memory film located in the opening;

a contiguous semiconductor material portion located over the memory film in the opening and comprising a semiconductor channel that includes a portion that extends substantially perpendicular to the top surface of the substrate; and

a metal semiconductor alloy region in contact with a bottom surface of the contiguous semiconductor material portion.

32. The three-dimensional memory device of claim 31, wherein the contiguous semiconductor material portion is electrically isolated from the substrate by the memory film.

33. The three-dimensional memory device of claim 32, wherein the metal semiconductor alloy region contacts a top surface of a horizontal portion of the memory film.

34. The three-dimensional memory device of claim 31, wherein the metal semiconductor alloy region comprises an alloy of a metal and a semiconductor material of the contiguous semiconductor material portion.

35. The three-dimensional memory device of claim 31, wherein the contiguous semiconductor material portion comprises a crystalline semiconductor material.

36. The three-dimensional memory device of claim 31, further comprising an integrated via and layer structure that comprises a vertical portion that extends through the stack and a horizontal portion that contacts a region of the contiguous semiconductor material portion and extending along a direction parallel to a top surface of the substrate.

37. The three-dimensional memory device of claim 36, wherein the electrically conductive layers are located above a level of the horizontal portion of the integrated via and layer structure.

38. The three-dimensional memory device of claim 37, wherein the region of the contiguous semiconductor material portion is a source region having electrical dopants of an opposite conductivity type than electrical dopants within the semiconductor channel.

39. The three-dimensional memory device of claim 31, wherein:

the three-dimensional memory device comprises a vertical NAND device located in a device region; and

at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, a word line of the vertical NAND device.

40. The three-dimensional memory device of claim 39, wherein the memory film comprises:

a tunneling dielectric in contact with the semiconductor channel;

at least one charge storage element contacting the tunneling dielectric; and

at least one blocking dielectric layer in contact with the at least one charge storage element.

41. The three-dimensional memory device of claim 39, wherein:

the device region comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;

the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including a plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.