SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR MANUFACTURING PROCESS

• US 20160233292A1
• Filed: 02/10/2015
• Published: 08/11/2016
• Est. Priority Date: 02/10/2015
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: CHEN, Chi-Han
• GRANTED PATENT: US 9,443,921 B2
• Time in patent office: 0 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73227 Wire and HDI connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/26 : Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1421 : RF devices
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

The present disclosure relates to a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure comprises a first dielectric layer, a die pad, an active component, at least one first metal bar, at least one second metal bar and a through via. The first dielectric layer has a first surface and a second surface opposite to the first surface. The die pad is located within the first dielectric layer. The active component is located within the first dielectric layer and disposed on the die pad. The first metal bar is disposed on the first surface of the first dielectric layer, and electrically connected to the active component. The second metal bar is disposed on the second surface of the first dielectric layer. The through via penetrates the first dielectric layer and connects the at least one first metal bar to the at least one second metal bar.

Claims

1. A semiconductor package structure, comprising:

a first dielectric layer having a first surface and a second surface opposite to the first surface;

a die pad within the first dielectric layer;

an active component within the first dielectric layer and disposed on the die pad;

a plurality of first metal bars disposed on the first surface of the first dielectric layer, the plurality of first metal bars being substantially parallel to each other, and at least one of the plurality of first metal bars being electrically connected to the active component;

a plurality of second metal bars disposed on the second surface of the first dielectric layer, the plurality of second metal bars being substantially parallel to each other; and

a plurality of through vias penetrating the first dielectric layer and connecting each of the plurality of first metal bars to a corresponding second metal bar.

2. The semiconductor package structure of claim 1, wherein the plurality of first metal bars, the plurality of second metal bars and the plurality of through vias together form an inductor.

3. The semiconductor package structure of claim 1, wherein the plurality of first metal bars are not parallel to the plurality of second metal bars.

4. The semiconductor package structure of claim 1, wherein

each of the plurality of first metal bars is arranged in a first direction;

each of the plurality of second metal bars is arranged in a second direction; and

the first direction is different from the second direction.

5. The semiconductor package structure of claim 1, further comprising a plurality of leads within the first dielectric layer.

6. The semiconductor package structure of claim 5, further comprising:

a first set of metal contacts being disposed on the first surface of the first dielectric layer and electrically connected to the plurality of leads;

a first set of vias within the first dielectric layer and electrically connecting the first set of metal contacts to the active component.

7. The semiconductor package structure of claim 1, wherein

each through via has a downward-tapering upper portion and an upward-tapering bottom portion, and wherein a depth of the downward-tapering upper portion is different from a depth of the upward-tapering bottom portion.

8. The semiconductor package structure of claim 1, further comprising

a core surrounded by the plurality of through vias, wherein the core comprises a magnetic material.

9. A semiconductor package structure, comprising:

a first dielectric layer having a top surface;

a die within the first dielectric layer; and

a first spiral inductor within the first dielectric layer, at least one terminal of the first spiral inductor being electrically connected to the die,

wherein a central axis of the first spiral inductor is substantially parallel to the top surface of the first dielectric layer.

10. The semiconductor package structure of claim 9, wherein the first spiral inductor is arranged at a periphery of the die.

11. The semiconductor package structure of claim 9, wherein

the first spiral inductor has a first portion and a second portion, the first portion is exposed from the top surface of the first dielectric layer, and the second portion is exposed from the bottom surface of the first dielectric layer.

12. The semiconductor package structure of claim 11, further comprising

a second dielectric layer disposed on the top surface of the first dielectric layer and covering the first set of metal contacts and the first portion of the first spiral inductor.

13. The semiconductor package structure of claim 12, further comprising:

a second set of metal contacts disposed on a top surface of the second dielectric layer; and

a second set of vias within the second dielectric layer and electrically connecting the second set of metal contacts to one or more of the first set of metal contacts.

14. The semiconductor package structure of claim 9, further comprising a second spiral inductor electrically connected to the die.

15. The semiconductor package structure of claim 9, further comprising:

a metal layer disposed on the bottom surface of the first dielectric layer; and

a third set of vias connecting the metal layer to the die pad.

16. The semiconductor package structure of claim 9, further comprising a core surrounded by the first spiral inductor, wherein the core comprises magnetic material.

17. A method of manufacturing a semiconductor package structure, comprising:

(a) providing a die pad;

(b) placing an active component on the die pad;

(c) forming a first dielectric layer to encapsulate the die pad and the active component, the first dielectric layer having a first surface and a second surface opposite the first surface;

(d) forming a plurality of through vias in the first dielectric material, the plurality of through vias exposed from the first surface and the second surface of the first dielectric layer;

(e) forming a first set of metal bars on the first surface of the first dielectric layer to connect to the plurality of through vias; and

(f) forming a second set of metal bars on the second surface of the first dielectric layer to connect to the plurality of through vias.

18. The method of claim 17, wherein forming a plurality of through vias in (d) further comprises:

forming a plurality of first openings from the first surface of the first dielectric layer without penetrating through to the second surface of the first dielectric layer;

plating a metal in the first openings to form first conductive vias;

forming a plurality of second openings from the second surface of the first dielectric layer to expose the first conductive vias;

plating a metal in the second openings to form second conductive vias, the second conductive vias connecting to the first conductive vias in the first dielectric layer.

19. The method of claim 17, wherein

each of the first set of metal bars is arranged in a first direction;

each of the second set of metal bars is arranged in a second direction; and

the first direction is different from the second direction.

20. The method of claim 17, further comprising:

forming a first set of vias within the first dielectric layer to electrically connect to the active component; and

forming a first set of metal contacts on the first surface of the first dielectric layer to electrically connect to the first set of vias.