PREFETCHING DATA
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Accused Products
Abstract
A prefetch controller is configured to communicate with a prefetch cache in order to increase system performance. The prefetch controller includes an instruction lookup table (ILT) configured to receive a first tuple including a first instruction ID and a first missed data address. The prefetch controller further includes a tuple history queue (THQ) configured to receive an instruction/stride tuple, the instruction/stride tuple generated by subtracting a last data access address from the first missed data address. The prefetch controller further includes a sequence prediction table (SPT) in communication with the tuple history queue (THQ) and the instruction lookup table. The prefetch controller includes an adder in communication with the instruction lookup table (ILT) and the sequence prediction table (SPT) configured to generate a predicted prefetch address and to provide the predicted prefetch address to a prefetch cache.
0 Citations
40 Claims
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1-20. -20. (canceled)
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21. A computer hardware system, comprising:
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a data cache; a prefetch controller configured to receive an initial tuple including an initial instruction ID and an initial missed data address, retrieve a last data access address, subtract the last data access address from the initial missed data address to generate an instruction/stride tuple, generate a predicted prefetch address using the instruction/stride tuple; and a prefetch cache configured to receive, from the prefetch controller, the predicted prefetch address, and provide, to the data cache, the predicted prefetch address. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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28. A computer-implemented method, comprising:
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receiving, by a prefetch controller, an initial tuple including an initial instruction ID and an initial missed data address; retrieving, by the prefetch controller, a last data access address; subtracting, by the prefetch controller, the last data access address from the initial missed data address to generate an instruction/stride tuple; generating, by the prefetch controller, a predicted prefetch address using the instruction/stride tuple; receiving, by a prefetch cache and from the prefetch controller, the predicted prefetch address, and providing, to the data cache and by the prefect cache, the predicted prefetch address. - View Dependent Claims (29, 30, 31, 32, 33, 34)
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35. A prefetch controller within a computer hardware system including a data cache and a prefetch cache, comprising:
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an instruction lookup table (ILT) configured to receive an initial tuple including an initial instruction ID and an initial missed data address; a tuple history queue (THQ) configured to receive an instruction/stride tuple generated by subtracting a last data access address from the initial missed data address; a sequence prediction table (SPT) in communication with the instruction lookup table (ILT) and the tuple history queue (THQ); an adder in communication with the instruction lookup table (ILT) and sequence prediction table (SPT) and configured to generate a predicted prefetch address using the instruction/stride tuple, and provide, to the prefetch cache, the predicted prefetch address, wherein the prefetch cache is configured to provide, to the data cache, the predicted prefetch address. - View Dependent Claims (36, 37, 38, 39, 40)
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Specification