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PIXEL STRUCTURE HAVING HIGH APERTURE RATIO AND CIRCUIT

  • US 20160247869A1
  • Filed: 09/19/2014
  • Published: 08/25/2016
  • Est. Priority Date: 09/02/2014
  • Status: Active Grant
First Claim
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1. A pixel structure having high aperture ratio, comprising a substrate, a first gate and a second gate, located at one side of the substrate;

  • a gate isolation layer, located on the first, the second gates and the gate isolation layer, and the gate isolation layer completely covers the first gate and the substrate, and exposes two ends of the second gate;

    a first semiconductor layer, located on the gate isolation layer and right over the first gate;

    a second semiconductor layer, located on the gate isolation layer and right over the second gate;

    an etching stopper layer, located on the first, the second semiconductor layer and the gate isolation layer;

    a first source/a first drain, located on the first semiconductor layer and the etching stopper layer;

    a second source/a second drain, located on the second semiconductor layer and the etching stopper layer, and the first source/the first drain are connected to the first semiconductor layer and one end of the second gate, and the second source/the second drain are connected to the second semiconductor layer;

    a protective layer, located on the first source/the first drain, the second source/the second drain and the etching stopper layer;

    a transparent electrode, located on the protective layer and at the other side of the substrate, and the transparent electrode is connected to the other end of the second gate;

    a flat isolation layer, located on the protective layer and the transparent electrode;

    a pixel electrode, located on the flat isolation layer, and the pixel electrode is connected to the second source/the second drain and overlaps with the transparent electrode;

    a pixel definition layer, located on the flat isolation layer and the pixel electrode, and the pixel definition layer comprises an open corresponding to an overlapping district of the pixel electrode and the transparent electrode;

    the first gate, the first source/the first drain, and the etching stopper layer, the first semiconductor layer, the gate isolation layer sandwiched in-between construct a first thin film transistor;

    the second gate, the second source/the second drain, and the etching stopper layer, the second semiconductor layer, the gate isolation layer sandwiched in between construct a second thin film transistor;

    the transparent electrode, the pixel electrode and the flat isolation layer sandwiched in-between construct a transparent capacitor.

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