SEMICONDUCTOR IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME

• US 20160255296A1
• Filed: 05/09/2016
• Published: 09/01/2016
• Est. Priority Date: 06/02/2005
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Iwabuchi, Shin, Motoyoshi, Makoto
• Granted Patent: US 10,594,972 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/14607 Geometry of the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 : MOS based technologies
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 29/788 : with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1425 : Converter
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1443 : Non-volatile random-access memory [NVRAM]
• CPC Class Codes: H04N 23/54 : Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/79 : Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Claims

1. An imaging device, comprising:

a first substrate including;

a pixel array unit including a first plurality of pixels arranged in a first direction, the first plurality of pixels including a first pixel configured to output a first analog signal, and a second plurality of pixels arranged in the first direction, the second plurality of pixels including a second pixel configured to output a second analog signal,

a driver circuit configured to drive the first plurality of pixels and the second plurality of pixels, the drive circuit being adjacent to the pixel array unit in a second direction that is different from the first direction, and

a plurality of signal lines extending along the first direction, the plurality of signal lines including a first signal line coupled to the first plurality of pixels and a second signal line coupled to the second plurality of pixels; and

a second substrate including;

a first analog to digital converter configured to receive the first analog signal via the first signal line, and

a second analog to digital converter configured to receive the second analog signal via the second signal line,

wherein the first substrate is laminated to the second substrate.

2. The imaging device according to claim 1, wherein the first analog to digital converter is configured to receive the first analog signal via a connection portion.

3. The imaging device according to claim 1, the first signal line coupled to the first analog to digital converter via a first connection portion and the second signal line coupled to the second analog to digital converter via a second connection portion.

4. The imaging device according to claim 2, wherein the connection portion is disposed between the first substrate and the second substrate.

5. The imaging device according to claim 1, wherein the first analog to digital converter includes a first comparator and a first counter, and the second analog to digital converter includes a second comparator and a second counter.

6. The imaging device according to claim 5, further comprising a reference signal generation circuit configured to output a reference signal to the first comparator and the second comparator.

7. The imaging device according to claim 6, wherein the first comparator is configured to compare the first analog signal and the reference signal, and the second comparator is configured to compare the second analog signal and the reference signal.

8. The imaging device according to claim 1, wherein the second substrate includes a reference signal generation circuit configured to output a reference signal.

9. The imaging device according to claim 1, wherein the first analog to digital converter is adjacent to the second analog to digital converter.

10. The imaging device according to claim 1, wherein the first plurality of pixels is adjacent to the second plurality of pixels in the second direction.

11. The imaging device according to claim 1, further comprising a timing control circuit configured to output a control signal to the driver circuit.

12. The imaging device according to claim 1, wherein the first pixel includes a first photoelectric conversion element, a first transfer transistor, a first reset transistor, a first amplifier transistor, and a first select transistor.

13. The imaging device according to claim 12, wherein the second pixel includes a second photoelectric conversion element, a second transfer transistor, a second reset transistor, a second amplifier transistor, and a second select transistor.

14. The imaging device according to claim 1, wherein the first pixel includes a plurality of first photoelectric conversion elements that share a first reset transistor, a first amplifier transistor, and a first select transistor.

15. The imaging device according to claim 14, wherein the second pixel includes a plurality of second photoelectric conversion elements that share a second reset transistor, a second amplifier transistor, and a second select transistor.

16. An imaging device, comprising:

a first substrate including;

a pixel array unit including a first plurality of pixels arranged in a first direction, the first plurality of pixels including a first pixel configured to output a first analog signal, and a second plurality of pixels arranged in the first direction, the second plurality of pixels including a second pixel configured to output a second analog signal,

a driver circuit configured to drive the first plurality of pixels and the second plurality of pixels, the drive circuit being adjacent to the pixel array unit in a second direction that is different from the first direction, and

a plurality of signal lines extending along the first direction, the plurality of signal lines including a first signal line coupled to the first plurality of pixels and a second signal line coupled to the second plurality of pixels; and

a second substrate including;

a first electronic processing circuit configured to receive the first analog signal via the first signal line, and

a second electronic processing circuit configured to receive the second analog signal via the second signal line,

wherein the first substrate is laminated to the second substrate.

17. The imaging device according to claim 16, wherein the first electronic processing circuit includes a portion of a first analog to digital converter.

18. The imaging device according to claim 17, wherein the second electronic processing circuit includes a portion of a second analog to digital converter.

19. The imaging device according to claim 18, wherein the first analog to digital converter includes a first comparator and a first counter, and the second analog to digital converter includes a second comparator and a second counter.

20. The imaging device according to claim 19, further comprising a reference signal generation circuit configured to output a reference signal to the first comparator and the second comparator.

21. The imaging device according to claim 16, wherein the first analog to digital converter is configured to receive the first analog signal via a connection portion.

22. The imaging device according to claim 20, wherein the connection portion is disposed between the first substrate and the second substrate.

23. The imaging device according to claim 16, wherein the second substrate includes a reference signal generation circuit configured to output a reference signal.

24. The imaging device according to claim 16, wherein the first electronic processing circuit is adjacent to the second electronic processing circuit.

25. The imaging device according to claim 16, wherein the first plurality of pixels is adjacent to the second plurality of pixels in the second direction.

26. The imaging device according to claim 16, further comprising a timing control circuit configured to output a control signal to the driver circuit.

27. The imaging device according to claim 16, wherein the first pixel includes a first photoelectric conversion element, a first transfer transistor, a first reset transistor, a first amplifier transistor, and a first select transistor, and the second pixel includes a second photoelectric conversion element, a second transfer transistor, a second reset transistor, a second amplifier transistor, and a second select transistor.

28. The imaging device according to claim 16, wherein the first pixel includes a plurality of first photoelectric conversion elements that share a first reset transistor, a first amplifier transistor, and a first select transistor.

30. The imaging device according to claim 16, wherein the first electronic processing circuit coupled to the first signal line via a first connection portion and the second electronic processing circuit coupled to the second signal line via a second connection portion.

29. The imaging device according to claim 29, wherein the second pixel includes a plurality of second photoelectric conversion elements that share a second reset transistor, a second amplifier transistor, and a second select transistor.