ESD PROTECTION STRUCTURE AND METHOD OF FABRICATION THEREOF

• US 20160276332A1
• Filed: 08/19/2015
• Published: 09/22/2016
• Est. Priority Date: 03/19/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: LAINE, Jean Philippe, BESSE, Patrice
• Granted Patent: US 10,037,986 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 29/66393 Lateral or planar thyristors
• CPC Class Codes: H01L 29/735 Lateral transistors
• CPC Class Codes: H01L 29/7436 Lateral thyristors
• CPC Class Codes: H01L 29/861 Diodes

Abstract

An ESD protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second semiconductor region of the first doping type, and a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the semiconductor regions of the first doping type and isolation between the further semiconductor region of the first doping type and the isolation trench. The semiconductor structure of the second doping type is formed such that no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, and no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.

Claims

1. An electrostatic discharge, ESD, protection structure;

the ESD protection structure being formed within an isolation trench recessed within a semiconductor substrate of an integrated circuit device and comprising;

a first semiconductor region of a first doping type, the first semiconductor region of the first doping type comprising a peripheral region of the first doping type,

a second semiconductor region of the first doping type, and

at least one semiconductor structure of a second doping type opposite to the first doping type formed to provide;

lateral isolation between the semiconductor regions of the first doping type, and

isolation between the second semiconductor region of the first doping type and the isolation trench;

the at least one semiconductor structure of the second doping type is formed such that;

no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, said peripheral side of the first semiconductor region of the first doping type being distal from the second semiconductor region of the first doping type, and

no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.

2. The ESD protection structure of claim 1, further comprising at least one well region of the first doping type formed within a surface of the first semiconductor region of the first doping type, the surface of the first semiconductor region of the first doping type being co-planar with a surface of the semiconductor substrate, the at least one well region of the first doping type abutting the wall of the isolation trench.

3. The ESD protection structure of claim 1, comprising no semiconductor region of the second doping type formed between the first semiconductor region of the first doping type and the isolation trench.

4. The ESD protection structure of claim 3, further comprising one of a uniform PN junction and a uniform NP junction formed between the first semiconductor region of the first doping type and the at least one semiconductor structure of the second doping type.

5. The ESD protection structure of claim 1, wherein the at least one semiconductor structure of the second doping type comprises:

at least one deep-well structure providing lateral isolation between the semiconductor regions of the first doping type and lateral isolation between the second semiconductor region of the first doping type and the isolation trench, and

a buried layer of the second doping type providing isolation between at least the second semiconductor region of the first doping type and a floor of the isolation trench.

6. The ESD protection structure of claim 1, wherein the first and second semiconductor regions of the first doping type are formed within an epitaxial layer within the semiconductor substrate.

7. The ESD protection structure of claim 1, wherein the isolation trench comprises:

a buried oxide, BOX, layer formed to provide a floor of the isolation trench, and

at least one deep trench isolation, DTI, formation formed to provide walls of the isolation trench.

8. An integrated circuit device comprising at least one semiconductor substrate comprising at least one electrostatic discharge, ESD, protection structure;

the ESD protection structure being formed within an isolation trench recessed within a semiconductor substrate of an integrated circuit device and comprising;

a first semiconductor region of a first doping type, the first semiconductor region of the first doping type comprising a peripheral region of the first doping type,

a second semiconductor region of the first doping type, and

at least one semiconductor structure of a second doping type opposite to the first doping type formed to provide;

lateral isolation between the semiconductor regions of the first doping type, and

isolation between the second semiconductor region of the first doping type and the isolation trench;

the at least one semiconductor structure of the second doping type is formed such that;

no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, said peripheral side of the first semiconductor region of the first doping type being distal from the second semiconductor region of the first doping type, and

no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.

9. The ESD protection structure of claim 8, further comprising at least one well region of the first doping type formed within a surface of the first semiconductor region of the first doping type, the surface of the first semiconductor region of the first doping type being co-planar with a surface of the semiconductor substrate, the at least one well region of the first doping type abutting the wall of the isolation trench.

10. The ESD protection structure of claim 8, comprising no semiconductor region of the second doping type formed between the first semiconductor region of the first doping type and the isolation trench.

11. The ESD protection structure of claim 10, further comprising one of a uniform PN junction and a uniform NP junction formed between the first semiconductor region of the first doping type and the at least one semiconductor structure of the second doping type.

12. The ESD protection structure of claim 8, wherein the at least one semiconductor structure of the second doping type comprises:

at least one deep-well structure providing lateral isolation between the semiconductor regions of the first doping type and lateral isolation between the second semiconductor region of the first doping type and the isolation trench, and

a buried layer of the second doping type providing isolation between at least the second semiconductor region of the first doping type and a floor of the isolation trench.

13. The ESD protection structure of claim 8, wherein the first and second semiconductor regions of the first doping type are formed within an epitaxial layer within the semiconductor substrate.

14. The ESD protection structure of claim 8, wherein the isolation trench comprises:

a buried oxide, BOX, layer formed to provide a floor of the isolation trench, and

at least one deep trench isolation, DTI, formation formed to provide walls of the isolation trench.

15. A method of fabricating an electrostatic discharge, ESD, protection structure within a semiconductor substrate of an integrated circuit device;

the method comprising;

forming an isolation trench recessed within the semiconductor substrate for containing the ESD protection structure,

forming a first semiconductor region of a first doping type, the first semiconductor region of the first doping type comprising a peripheral region of the first doping type,

forming a second semiconductor region of the first doping type, and

forming at least one semiconductor structure of a second doping type opposite to the first doping type formed to provide;

lateral isolation between the semiconductor regions of the first doping type, and

isolation between the second semiconductor region of the first doping type and the isolation trench;

the at least one semiconductor structure of the second doping type is formed such that;

no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, said peripheral side of the first semiconductor region of the first doping type being distal from the second semiconductor region of the first doping type, and

no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.

16. The method of claim 15, further comprising forming at least one well region of the first doping type within a surface of the first semiconductor region of the first doping type, the surface of the first semiconductor region of the first doping type being co-planar with a surface of the semiconductor substrate, the at least one well region of the first doping type abutting the wall of the isolation trench.

17. The method of claim 15, further comprising forming no semiconductor region of the second doping type between the first semiconductor region of the first doping type and the isolation trench.

18. The method of claim 15, further comprising forming one of a uniform PN junction and a uniform NP junction between the first semiconductor region of the first doping type and the at least one semiconductor structure of the second doping type.

19. The method of claim 15, further comprising forming the at least one semiconductor structure of the second doping type to comprise:

at least one deep-well structure providing lateral isolation between the semiconductor regions of the first doping type and lateral isolation between the second semiconductor region of the first doping type and the isolation trench; and

a buried layer of the second doping type providing isolation between at least the second semiconductor region of the first doping type and a floor of the isolation trench.

20. The method of claim 15, further comprising forming the first and second semiconductor regions of the first doping type within an epitaxial layer within the semiconductor substrate.