SYSTEM POWER MANAGEMENT USING COMMUNICATION BUS PROTOCOLS

• US 20160291685A1
• Filed: 06/16/2016
• Published: 10/06/2016
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Warren, David S., Levit, Inna, Paaske, Timothy R.
• Granted Patent: US 10,551,907 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Claims

1. An apparatus coupled to a communication bus, wherein the apparatus comprises:

one or more functional blocks; and

a control circuit configured to;

monitor a level of activity;

send a message on the communication bus dependent upon the level of activity, wherein the message includes data indicative of a time to resume operation after activation of a low power mode; and

activate the lower power mode dependent upon a response to the message.

2. The apparatus of claim 1, wherein to activate the low power mode, the control circuit is further configured to reduce a voltage level of a power supply coupled to at least one of the one or more functional blocks.

3. The apparatus of claim 1, further comprising a clock generation circuit configured to generate at least one clock signal, wherein the clock signal is coupled to at least one of the one or more functional blocks, and wherein to activate the low power mode, the control circuit is further configured to deactivate the at least one clock signal.

4. The apparatus of claim 1, wherein the data indicative of the time to resume operation after activation of the low power mode includes a scale value.

5. The apparatus of claim 1, further comprising an interface unit coupled to the communication bus, and wherein to activate the low power mode, the control circuit is further configured to deactivate the interface unit.

6. The apparatus of claim 1, wherein the clock generation circuit includes a phase-locked loop (PLL).

7. A method for operating a computing system including one or more functional blocks, the method comprising:

monitoring a level of activity of the computing system;

sending a message on a communication bus dependent upon the level of activity, wherein the message includes data indicative of a time to resume operation after activation of a low power mode;

activate the lower power mode dependent upon a response to the message.

8. The method of claim 7, wherein activating the low power mode includes reducing a voltage level of a power supply coupled to at least one of the one or more functional blocks.

9. The method of claim 7, wherein activating the low power mode includes deactivating at least one clock signal, wherein the at least one clock signal is coupled to at least one of the one or more functional blocks.

10. The method of claim 7, wherein the data indicative of the time to resume operation after activation of the low power mode includes a scale value.

11. The method of claim 10, further comprising determining the response dependent upon a product of the data indicative of the time to resume operation and the scale value.

12. The method of claim 11, further comprising comparing the product of the data indicative of a time to resume operation and the scale value to a predetermined threshold value.

13. The method of claim 7, wherein to activating the low power mode includes deactivating an interface unit included in the computing system.

14. A system, comprising:

a host; and

a device configured to;

monitor a level of activity;

send a message to the host dependent upon the level of activity, wherein the message includes data indicative of a time to resume operation after activation of a low power mode; and

activate the lower power mode dependent upon a response to the message received from the host.

15. The system of claim 14, wherein the device includes one or more functional blocks, and wherein to activate the low power mode, the device is further configured to reduce a voltage level of a power supply coupled to at least one of the one or more functional blocks.

16. The system of claim 14, wherein the device includes one or more functional blocks, wherein a given one of the one or more functional blocks includes a clock generation circuit configured to generate at least one clock signal, wherein the clock signal is coupled to at least one of the one or more functional blocks, and wherein to activate the low power mode, the device is further configured to deactivate the at least one clock signal.

17. The system of claim 16, wherein the clock generation circuit includes a phase-locked loop (PLL).

18. The system of claim 14, wherein the data indicative of the time to resume operation after activation of the low power mode includes a scale value.

19. The system of claim 14, wherein the device is coupled to the host via a communication bus, wherein the device includes an interface unit coupled to the communication bus, and wherein to activate the low power mode, the device is further configured to deactivate the interface unit.

20. The system of claim 14, wherein the host is configured to message dependent upon the data indicative of the time to resume operation after activation of the low power mode and the scale value.