MEMORY UNIT WITH VOLTAGE PASSING DEVICE

• US 20160293261A1
• Filed: 03/10/2016
• Published: 10/06/2016
• Est. Priority Date: 04/01/2015
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Chen, Chih-Hsin, Wang, Shih-Chen, Lai, Tsung-Mu
• Granted Patent: US 9,524,785 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer

Abstract

A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate transistor has a first terminal for receiving a bit line signal, a second terminal, and a floating gate. The word line transistor has a first terminal coupled to the second terminal of the floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal. A voltage passing device is for outputting a second voltage during an inhibit operation and a first voltage during a program operation or an erase operation. The first capacitance element is coupled to the first voltage passing device and the floating gate, and for receiving a first control signal. The second capacitance element is for receiving at a second control signal.

Claims

1. A memory unit, comprising:

a first voltage passing device configured to output voltages according to operations of the memory unit; and

a first memory cell comprising;

a first floating gate transistor having a first terminal configured to receive a first bit line signal, a second terminal, and a floating gate; and

a first capacitance element having a first terminal coupled to the first voltage passing device, a second terminal, a control terminal coupled to the floating gate of the first floating gate transistor, and a body configured to receive a first control signal;

wherein;

the first capacitance element and the first voltage passing device are disposed in a first N-well;

the first terminal of the first capacitance element receives a first voltage outputted from the first voltage passing device during a program operation or an erase operation of the first memory cell and receives a second voltage outputted from the first voltage passing device during an inhibit operation of the first memory cell; and

the first voltage is greater than the second voltage.

2. The memory unit of claim 1, wherein the first voltage passing device comprises:

a first passing gate transistor having a first terminal configured to receive an inhibit signal, a second terminal coupled to the first terminal of the first capacitance element, and a control terminal configured to receive a passing gate control signal.

3. The memory unit of claim 2, wherein:

during the program operation of the memory unit, the first control signal is at the first voltage, the first bit line signal is in a range from a fourth voltage to a third voltage, the inhibit signal is at the first voltage, the passing gate control signal is at a fifth voltage, and the first terminal of the first passing gate transistor receives the first voltage;

during a program inhibit operation of the memory unit, the first control signal is at the first voltage, the first bit line signal is in a range from the fourth voltage to the third voltage, the inhibit signal is at the second voltage, the passing gate control signal is at the fifth voltage, and the first terminal of the first passing gate transistor receives the second voltage; and

the third voltage is smaller than the fourth voltage, the fourth voltage is smaller than the fifth voltage, and the fifth voltage is smaller than the second voltage.

4. The memory unit of claim 3, wherein the first memory cell further comprises:

a first word line transistor having a first terminal coupled to the second terminal of the first floating gate transistor, a second terminal configured to receive the third voltage, and a control terminal configured to receive a word line signal;

wherein;

during the program operation of the memory unit, the word line signal is in a range from the fourth voltage to the third voltage; and

during the program inhibit operation of the memory unit, the word line signal is in a range from the fourth voltage to the third voltage.

5. The memory unit of claim 4, wherein the first word line transistor has a low threshold voltage.

6. The memory unit of claim 3, wherein the first memory cell further comprises:

a second capacitance element coupled to the floating gate of the first floating gate transistor and configured to receive at least a second control signal;

wherein;

during the program operation of the memory unit, the second control signal is at the first voltage; and

during the program inhibit operation of the memory unit, the second control signal is at the first voltage.

7. The memory unit of claim 2, wherein:

during the erase operation of the memory unit, the first control signal is at the first voltage, the first bit line signal is in a range from a fourth voltage to a third voltage, the inhibit signal is at the first voltage, the passing gate control signal is at a fifth voltage, and the first terminal of the first passing gate transistor receives the first voltage;

during an erase inhibit operation of the memory unit, the first control signal is at the first voltage, the first bit line signal is in a range from the fourth voltage to the third voltage, the inhibit signal is at the second voltage, the passing gate control signal is at the fifth voltage, and the first terminal of the first passing gate transistor receives the second voltage; and

the third voltage is smaller than the fourth voltage, the fourth voltage is smaller than the fifth voltage, and the fifth voltage is smaller than the second voltage.

8. The memory unit of claim 7, wherein the first memory cell further comprises:

a first word line transistor having a first terminal coupled to the second terminal of the first floating gate transistor, a second terminal configured to receive the third voltage, and a control terminal configured to receive a word line signal;

wherein;

during the erase operation of the memory unit, the word line signal is in a range from the fourth voltage to the third voltage; and

during the erase inhibit operation of the memory unit, the word line signal is in a range from the fourth voltage to the third voltage.

9. The memory unit of claim 8, wherein the first word line transistor has a low threshold voltage.

10. The memory unit of claim 7, wherein the first memory cell further comprises:

a second capacitance element coupled to the floating gate of the first floating gate transistor and configured to receive at least a second control signal;

wherein;

during the erase operation of the memory unit, the second control signal is at the third voltage; and

during the erase inhibit operation of the memory unit, the second control signal is at the third voltage.

11. The memory unit of claim 1, wherein the first voltage passing device comprises:

a first passing gate transistor having a first terminal configured to receive an inhibit signal, a second terminal coupled to the first terminal of the first capacitance element, and a control terminal configured to receive a first passing gate control signal; and

a second passing gate transistor having a first terminal coupled to the second terminal of the first capacitance element, a second terminal configured to receive the first voltage or the first control signal, and a control terminal configured to receive a second passing gate control signal.

12. The memory unit of claim 11, wherein:

during the program operation of the memory unit, the first control signal is at the first voltage, the first bit line signal is in a range from a fourth voltage to a third voltage, the inhibit signal is at the second voltage, the first passing gate control signal is at the first voltage, and the second passing gate control signal is at a fifth voltage;

during a program inhibit operation of the memory unit, the first control signal is at the first voltage, the first bit line signal is in a range from the fourth voltage to the third voltage, the inhibit signal is at the second voltage, the first passing gate control signal is at the fifth voltage, and the second passing gate control signal is at the first voltage; and

the third voltage is smaller than the fourth voltage, the fourth voltage is smaller than the fifth voltage, and the fifth voltage is smaller than the second voltage.

13. The memory unit of claim 12, wherein the first memory cell further comprises:

a first word line transistor having a first terminal coupled to the second terminal of the first floating gate transistor, a second terminal configured to receive the third voltage, and a control terminal configured to receive a word line signal;

wherein;

during the program operation of the memory unit, the word line signal is in a range from the fourth voltage to the third voltage; and

during the program inhibit operation of the memory unit, the word line signal is in a range from the fourth voltage to the third voltage.

14. The memory unit of claim 12, wherein the first memory cell further comprises:

a second capacitance element coupled to the floating gate of the first floating gate transistor and configured to receive at least a second control signal;

wherein;

during the program operation of the memory unit, the second control signal is at the first voltage; and

during the program inhibit operation of the memory unit, the second control signal is at the first voltage.

15. The memory unit of claim 11, wherein:

during the erase operation of the memory unit, the first control signal is at the first voltage, the first bit line signal is in a range from a fourth voltage to a third voltage, the inhibit signal is at the second voltage, the first passing gate control signal is at the first voltage, and the second passing gate control signal is at a fifth voltage;

during an erase inhibit operation of the memory unit, the first control signal is at the first voltage, the first bit line signal is in a range from the fourth voltage to the third voltage, the inhibit signal is at the second voltage, the first passing gate control signal is at the fifth voltage, and the second passing gate control signal is at the first voltage; and

the third voltage is smaller than the fourth voltage, the fourth voltage is smaller than the fifth voltage, and the fifth voltage is smaller than the second voltage.

16. The memory unit of claim 15, wherein the first memory cell further comprises:

a first word line transistor having a first terminal coupled to the second terminal of the first floating gate transistor, a second terminal configured to receive the third voltage, and a control terminal configured to receive a word line signal;

wherein;

during the program operation of the memory unit, the word line signal is in a range from the fourth voltage to the third voltage; and

during the program inhibit operation of the memory unit, the word line signal is in a range from the fourth voltage to the third voltage.

17. The memory unit of claim 15, wherein the first memory cell further comprises:

a second capacitance element coupled to the floating gate of the first floating gate transistor and configured to receive at least a second control signal;

wherein;

during the program operation of the memory unit, the second control signal is at the first voltage; and

during the program inhibit operation of the memory unit, the second control signal is at the first voltage.

18. The memory unit of claim 11, wherein:

the first memory cell further comprises;

a first word line transistor having a first terminal coupled to the second terminal of the first floating gate transistor, a second terminal configured to receive a third voltage, and a control terminal configured to receive a word line signal; and

a second capacitance element coupled to the floating gate of the first floating gate transistor and configured to receive at least a second control signal; and

the memory unit further comprises;

a second voltage passing device, comprising;

a third passing gate transistor having a first terminal configured to receive the inhibit signal, a second terminal, and a control terminal configured to receive the second passing gate control signal; and

a fourth passing gate transistor having a first terminal, a second terminal configured to receive the first voltage or the first control signal, and a control terminal configured to receive the first passing gate control signal; and

a second memory cell, comprising;

a third capacitance element coupled to the second terminal of the third passing gate transistor and the first terminal of the fourth passing gate transistor, and configured to receive the first control signal and voltages outputted from the second voltage passing device;

a fourth capacitance element configured to receive the second control signal;

a second floating gate transistor having a first terminal configured to receive a second bit line signal, a second terminal, and a floating gate coupled to the third capacitance element and the fourth capacitance element; and

a second word line transistor having a first terminal coupled to the second terminal of the second floating gate transistor, a second terminal configured to receive the third voltage, and a control terminal configured to receive the word line signal.

19. The memory unit of claim 1, further comprising:

N additional memory cells, each comprising;

an additional first capacitance element;

an additional second capacitance element;

an additional floating gate transistor having a first terminal configured to receive a corresponding bit line signal, a second terminal, and a floating gate coupled to the additional first capacitance element and the additional second capacitance element; and

an additional word line transistor having a first terminal coupled to the second terminal of the additional floating gate transistor, a second terminal configured to receive a third voltage, and a control terminal configured to receive a corresponding word line signal;

wherein N is a positive integer.

20. The memory unit of claim 19, wherein:

the first voltage passing device comprises a first passing gate transistor having a first terminal configured to receive an inhibit signal, a second terminal coupled to the first terminal of the first capacitance element, and a control terminal configured to receive a passing gate control signal; and

N additional first capacitance elements of the N additional memory cells are coupled in series with the first capacitance element.

21. The memory unit of claim 19, wherein:

the first voltage passing device comprises a first passing gate transistor having a first terminal configured to receive an inhibit signal, a second terminal coupled to the first terminal of the first capacitance element, and a control terminal configured to receive a passing gate control signal; and

the additional first capacitance element has a first terminal coupled to the first terminal of the first capacitance element, a second terminal coupled to the second terminal of the first capacitance element, and a control terminal coupled to the floating gate of the additional floating gate transistor.

22. The memory unit of claim 19, wherein:

the first voltage passing device comprises;

a first passing gate transistor having a first terminal configured to receive an inhibit signal, a second terminal coupled to the first terminal of the first capacitance element, and a control terminal configured to receive a first passing gate control signal; and

a second passing gate transistor having a first terminal, a second terminal configured to receive the first voltage or the first control signal, and a control terminal configured to receive a second passing gate control signal; and

N additional first capacitance elements of the N additional memory cells are coupled in series between the second terminal of the first capacitance element and the first terminal of the second passing gate transistor.

23. The memory unit of claim 19, wherein:

the first voltage passing device comprises;

a first passing gate transistor having a first terminal configured to receive an inhibit signal, a second terminal coupled to the first terminal of the first capacitance element, and a control terminal configured to receive a first passing gate control signal; and

a second passing gate transistor having a first terminal, a second terminal configured to receive the first voltage or the first control signal, and a control terminal configured to receive a second passing gate control signal; and

the additional first capacitance element has a first terminal coupled to the first terminal of the first capacitance element, a second terminal coupled to the first terminal of the second passing gate transistor, and a control terminal coupled to the floating gate of the additional floating gate transistor.

24. The memory unit of claim 1, further comprising:

a second voltage passing device configured to output the first voltage during the program operation or the erase operation of the memory unit and output the second voltage during the inhibit operation of the memory unit; and

a second capacitance element coupled to the floating gate of the first floating gate transistor and the second voltage passing device, and configured to receive voltages outputted from the second voltage passing device.

25. A memory array, comprising:

at least one row of memory units, each memory unit in a same row comprising;

a first voltage passing device configured to receive an inhibit signal, and output voltages according to a first passing gate control signal;

a second voltage passing device configured to receive the inhibit signal, and output voltages according to a second passing gate control signal;

a first memory cell, comprising;

a first floating gate transistor having a first terminal configured to receive a first bit line signal, a second terminal, and a floating gate;

a first capacitance element having a first terminal coupled to the first voltage passing device, a second terminal, a control terminal coupled to the floating gate of the first floating gate transistor, and a body configured to receive a first control signal;

a first word line transistor having a first terminal coupled to the second terminal of the first floating gate transistor, a second terminal configured to receive a third voltage, and a control terminal configured to receive a word line signal; and

a second capacitance element coupled to the floating gate of the first floating gate transistor, and configured to receive a second control signal; and

a second memory cell, comprising;

a second floating gate transistor having a first terminal configured to receive a second bit line signal, a second terminal, and a floating gate;

a third capacitance element having a first terminal coupled to the second voltage passing device, a second terminal, a control terminal coupled to the floating gate of the second floating gate transistor, and a body configured to receive the first control signal;

a second word line transistor having a first terminal coupled to the second terminal of the second floating gate transistor, a second terminal configured to receive the third voltage, and a control terminal configured to receive the word line signal; and

a fourth capacitance element coupled to the floating gate of the second floating gate transistor, and configured to receive the second control signal;

wherein;

memory units in a same row receive a same inhibit signal, a same first control signal, a same second control signal, and a same word line signal;

memory units in the same row receive different first bit line signals, different second bit line signals, different first passing gate control signals, and different second passing gate control signals.

26. The memory array of claim 25, wherein:

memory units indifferent rows receive different inhibit signals, different first control signals, different second control signals, and different word line signals; and

memory units indifferent rows but in a same column receive a same first bit line signal, a same second bit line signal, a same first passing gate control signal, and a same second passing gate control signal.