Electronic Circuit For Driving A Hall Effect Element With A Current Compensated For Substrate Stress

• US 20160299199A1
• Filed: 04/08/2015
• Published: 10/13/2016
• Est. Priority Date: 04/08/2015
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Cesaretti, Juan Manuel, Cook, Aaron
• Granted Patent: US 9,638,764 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 33/0023 Electronic aspects, e.g. circuits for stimulation, evaluation, control; Treating the measured signals; calibration G01R33/0017 takes precedence
• CPC Class Codes: G01R 33/0041 using feed-back or modulation techniques
• CPC Class Codes: G01R 33/0052 Manufacturing aspects; Manufacturing of single devices, i.e. of semiconductor magnetic sensor chips devices based on galvano-magnetic effect or the like H10N50/85
• CPC Class Codes: G01R 33/07 Hall effect devices
• CPC Class Codes: G01R 33/075 Hall devices configured for spinning current measurements

Abstract

An electronic circuit can be disposed upon a semiconductor substrate. An epitaxial layer can be disposed over the semiconductor substrate. The electronic circuit can include a Hall effect element, at least a portion of the Hall effect element disposed in the epitaxial layer. The electronic circuit can further include a current generator configured to generate a drive current that passes through the Hall effect element. The current generator can include a resistor disposed in the epitaxial layer and having characteristics such that a resistance of the resistor can vary with a stress of the semiconductor substrate, resulting in changes of the drive current, to compensate for variations in the sensitivity of the Hall effect element with the stress of the substrate.

Claims

1. An electronic circuit, comprising:

a semiconductor substrate having a surface;

an epitaxial layer disposed over the surface of the semiconductor substrate, the epitaxial layer having a first surface distal from the semiconductor substrate and a second surface proximate to the semiconductor substrate;

a Hall effect element, at least a portion of the Hall effect element disposed in the epitaxial layer, and

a current generator configured to generate a drive current that passes through the Hall effect element, wherein the current generator comprises;

a first resistor for receiving a reference voltage resulting in a reference current passing through the first resistor, the reference current related to the drive current, the first resistor disposed in the epitaxial layer, wherein a resistance of the first resistor, the reference current, and the drive current change in accordance with changes of a stress in the semiconductor substrate.

2. The electronic circuit of claim 1, wherein the first resistor comprises:

first and second pickups implanted upon and diffused into the first surface of the epitaxial layer; and

a first buried structure disposed under the first surface of the epitaxial layer and under the first and second pickups, wherein the first buried structure has a density of atoms that results in a first low resistance path with a first resistance lower than a resistance of the epitaxial layer, wherein the reference current passes from the first pickup, through a first region of the epitaxial layer, through the first buried structure, and through a second region of the epitaxial layer to the second pickup.

3. The electronic circuit of claim 2, wherein the reference current passes through the first and second regions of the epitaxial layer in a direction substantially perpendicular to the first surface of the epitaxial layer.

4. The electronic circuit of claim 3, wherein the first buried structure has a first length dimension and a first width dimension, the first length dimension parallel to the first surface of the epitaxial layer.

5. The electronic circuit of claim 4, wherein the first length dimension of the first buried structure is disposed parallel to a first edge of the Hall effect element and proximate to the Hall effect element.

6. The electronic circuit of claim 5, wherein the Hall effect element comprises a horizontal Hall effect element.

7. The electronic circuit of claim 2, wherein the reference current is generated in accordance with the reference voltage coupled to the first pickup of the first resistor.

8. The electronic circuit of claim 2, wherein the first resistor is coupled to an operational amplifier to form a current source or a current sink.

9. The electronic circuit of claim 8, further comprising a current mirror coupled to the operational amplifier, wherein the current mirror comprises a reference leg through which the reference current passes, and a drive leg through which the drive current passes, wherein the drive current passing through the Hall effect element passes between a higher voltage terminal of the Hall effect element and a lower voltage terminal of the Hall effect element

10. The electronic circuit of claim 9, wherein the drive leg of the current mirror is coupled to the higher voltage terminal.

11. The electronic circuit of claim 9, wherein the drive leg of the current mirror is coupled to the lower voltage terminal

12. The electronic circuit of claim 2, wherein the current generator further comprises:

a second resistor coupled in series or in parallel with the first resistor, the second resistor disposed in the epitaxial layer, wherein the second resistor comprises;

third and fourth pickups implanted upon and diffused into the first surface of the epitaxial layer; and

a second buried structure disposed under the first surface of the epitaxial layer and under the third and fourth pickups, wherein the second buried structure has the density of atoms that results in a second low resistance path with a second resistance lower than the resistance of the epitaxial layer, wherein at least a portion of the reference current passes from the third pickup, through a third region of the epitaxial layer, through the second buried structure, and through a fourth region of the epitaxial layer to the fourth pickup.

13. The electronic circuit of claim 12, wherein,

when the first and second resistors are coupled in parallel, a first portion of the reference current passes through the first and second regions of the epitaxial layer in a direction substantially perpendicular to the first surface of the epitaxial layer and a second portion of the reference current passes through the third and fourth regions of the epitaxial layer in the direction substantially perpendicular to the first surface of the epitaxial layer, and wherein,

when the first and second resistors are coupled in series, the reference current passes through the first, second, third, and fourth regions of the epitaxial layer in a direction substantially perpendicular to the first surface of the epitaxial layer.

14. The electronic circuit of claim 13, wherein the first buried structure has a first length dimension and a first width dimension, the first length dimension parallel to the first surface of the epitaxial layer, and wherein the second buried structure has a second length dimension and a second width dimension, the second length dimension parallel to the first surface of the epitaxial layer.

15. The electronic circuit of claim 14, wherein the first length dimension of the first buried structure is disposed parallel to a first edge of the Hall effect element and proximate to the Hall effect element, and wherein the second length dimension of the second buried structure is disposed parallel to a second edge of the Hall effect element and proximate to the Hall effect element, wherein the second length dimension of the second buried structure is arranged perpendicular to the first length dimension of the first buried structure.

16. The electronic circuit of claim 15, wherein the first and second resistors are coupled in series.

17. The electronic circuit of claim 15, wherein the first and second resistors are coupled in parallel.

18. The electronic circuit of claim 15, wherein the Hall effect element comprises a horizontal Hall effect element.

19. The electronic circuit of claim 12, wherein the reference current is generated in accordance with the reference voltage coupled to a series or parallel arrangement of the first and second resistors.

20. The electronic circuit of claim 12, wherein the first resistor and the second resistor are coupled to an operational amplifier to form a current source or a current sink.

21. The electronic circuit of claim 20, further comprising a current mirror coupled to the operational amplifier, wherein the current mirror comprises a reference leg through which the first portion and the second portion of the reference current pass, and a drive leg through which the drive current passes, wherein the drive current passing through the Hall effect element passes between a higher voltage terminal of the Hall effect element and a lower voltage terminal of the Hall effect element.

22. The electronic circuit of claim 21, wherein the drive leg of the current mirror is coupled to the higher voltage terminal.

23. The electronic circuit of claim 21, wherein the drive leg of the current mirror is coupled to the lower voltage terminal.

24. A method of biasing a Hall effect element, comprising:

generating a reference current by generating a voltage reference across a resistor disposed in an epitaxial layer over a semiconductor substrate, the epitaxial layer having a first surface distal from the semiconductor substrate and a second surface proximate to the semiconductor substrate; and

injecting a drive current into the Hall effect element, wherein the Hall effect element is disposed over the semiconductor substrate, wherein the drive current is related to the reference current, wherein a resistance of the resistor, the reference current, and the drive current change in accordance with changes of a stress in the semiconductor substrate.

25. The method of claim 24, wherein the resistor comprises:

first and second pickups implanted upon and diffused into the first surface of the epitaxial layer, and

a first buried structure disposed under the first surface of the epitaxial layer and under the first and second pickups, wherein the first buried structure has a density of atoms that results in a first low resistance path with a first resistance lower than a resistance of the epitaxial layer, wherein the reference current passes from the first pickup, through a first region of the epitaxial layer, through the first buried structure, and through a second region of the epitaxial layer to the second pickup.