Add-On Memory Coherence Directory

• US 20160321191A1
• Filed: 04/30/2015
• Published: 11/03/2016
• Est. Priority Date: 04/30/2015
• Status: Active Grant

• Current Assignee: Beijing Zitiao Network Technology Company Limited (ByteDance Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Daly, David M.
• Granted Patent: US 9,842,050 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/622 State-only directory, i.e. not recording identity of sharing or owning nodes

Abstract

A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.

Claims

1-13. -13. (canceled)

14. An apparatus comprising:

a processing chip in a multiprocessing data processing system;

wherein the processing chip comprises a plurality of processors;

wherein each processor within the plurality of processors comprises a processing core and a cache; and

wherein a given processor in the processing chip is configured to;

responsive to a memory access resulting in a cache miss in the given processor, determine whether a memory region being accessed is marked as directory-based;

responsive to the given processor determining the memory region is marked as directory-based, access a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol; and

forward the memory access request from the given processor to the home chip to perform the memory access.

15. The apparatus of claim 14, wherein the directory entry comprises a sharing vector, wherein the sharing vector comprises a bit vector having a bit for each chip in the multiple processor system and wherein each bit in the bit vector is asserted if the corresponding chip is sharing the memory region.

16. The apparatus of claim 14, wherein the memory access request is a load request and wherein the home chip forwards a read request to a sharing node, the sharing node services the read request, and the sharing node forwards data for the read request directly to the given processor.

17. The apparatus of claim 14, wherein the memory access request is a store request and wherein the given processor forwards a read with intent to modify (RWITM) request to the home chip, the home chip forwards the RWITM request and a number of sharers to a sharing node, the home chip sends invalidate notifications to the sharers, the sharing node services the RWITM request, and the sharing node forwards data for the RWITM request directly to the given processor.

18. The apparatus of claim 17, wherein the given processor in the processing chip is further configured to:

receive the data for the RWITM request and the number of sharers;

count confirmation notifications indicating the sharers have invalidated their copies of the data; and

responsive to the number of confirmation notifications equaling the number of sharers, send a final confirmation message to the home node.

19. The apparatus of claim 14, wherein the given processor in the processing chip is further configured to attempt to service the memory access locally using a directory protocol in parallel with forwarding the memory access request to the home chip to perform the directory-based memory access.

20. The apparatus of claim 14, wherein the given processor in the processing chip is further configured to perform the memory access using a snooping protocol responsive to the given processor determining the memory region is not marked as directory-based.

21. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:

responsive to a memory access resulting in a cache miss in a given processor, determine whether a memory region being accessed is marked as directory-based;

responsive to the given processor determining the memory region is marked as directory-based, access a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol; and

forward the memory access request from the given processor to the home chip to perform the memory access.