Via Definition Scheme
First Claim
Patent Images
1. A method, comprising:
- defining a conductive line pattern layer over a first dielectric layer, wherein the first dielectric layer is disposed over a second dielectric layer, and wherein an opening in the conductive line pattern layer exposes a first portion of the first dielectric layer, the first portion having a first width;
forming spacers along sidewalls of the opening, wherein after forming the spacers a second portion of the first dielectric layer is exposed, the second portion of the first dielectric layer having a second width;
etching the second portion of the first dielectric layer using the spacers as a mask to expose a portion of the second dielectric layer;
removing the spacers after etching the second portion of the first dielectric layer, the removing exposing third portions of the first dielectric layer;
etching the third portions of the first dielectric layer to form a trench in the first dielectric layer, the trench having the first width; and
etching the portion of the second dielectric layer to form a via hole in the second dielectric layer, the via hole having the second width.
0 Assignments
0 Petitions
Accused Products
Abstract
A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.
-
Citations
20 Claims
-
1. A method, comprising:
-
defining a conductive line pattern layer over a first dielectric layer, wherein the first dielectric layer is disposed over a second dielectric layer, and wherein an opening in the conductive line pattern layer exposes a first portion of the first dielectric layer, the first portion having a first width; forming spacers along sidewalls of the opening, wherein after forming the spacers a second portion of the first dielectric layer is exposed, the second portion of the first dielectric layer having a second width; etching the second portion of the first dielectric layer using the spacers as a mask to expose a portion of the second dielectric layer; removing the spacers after etching the second portion of the first dielectric layer, the removing exposing third portions of the first dielectric layer; etching the third portions of the first dielectric layer to form a trench in the first dielectric layer, the trench having the first width; and etching the portion of the second dielectric layer to form a via hole in the second dielectric layer, the via hole having the second width. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. An integrated circuit, comprising:
-
a metal line in a dielectric layer, the metal line having a linear portion and an enlarged area in a plan view; and a via extending from the metal line through an underlying dielectric layer, the via being completely below the enlarged area in the plan view. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. An integrated circuit comprising:
-
one or more dielectric layers; a metal line extending from a top of the one or more dielectric layers; and a via extending from the metal line to a bottom of the one or more dielectric layers, wherein a first portion of the metal line directly overlying the via has a width greater than a second portion of the metal line not directly overlying the via. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification