POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR

• US 20160329320A1
• Filed: 07/20/2016
• Published: 11/10/2016
• Est. Priority Date: 01/10/2004
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Inventors: Davies, Robert Bruce
• Granted Patent: US 9,865,590 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/83193 wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 23/047 the other leads being parallel to the base
• CPC Class Codes: H01L 23/051 another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/4824 : Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/49844 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0296 : involving a specific disposition of the protective devices
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 : specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 : characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/66681 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66719 : With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 : with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7817 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Claims

1. A semiconductor device comprising:

a semiconductor package including a plurality of transistors, wherein each transistor of the plurality of transistors has a gate, a drain region, and a source region;

a first lead adjacent to and in electrical communication with a first portion of a first surface of the semiconductor package;

a second lead in electrical communication with a second portion of the first surface of the semiconductor package;

a third lead adjacent to and in electrical communication with a second surface of the semiconductor package; and

a non-conductive material surrounding the semiconductor package, wherein the semiconductor package is within a sealed volume defined, at least in part, by the first lead, the third lead, and the non-conductive material.

2. The semiconductor device of claim 1, wherein the first surface of the semiconductor package is opposite from the second surface of the semiconductor package.

3. The semiconductor device of claim 1, wherein the first lead and the second lead are configured to conduct heat produced by the semiconductor package away from the semiconductor package.

4. The semiconductor device of claim 1, wherein the gates of the plurality of transistors are coupled to each other, wherein the first lead is in electrical communication with the source region of each of the plurality of transistors, wherein the second lead is in electrical communication with the gate of each of the plurality of transistors, and wherein the third lead is in electrical communication with the drain region of each of the plurality of transistors.

5. The semiconductor device of claim 1, wherein the second portion of the first surface surrounds the first portion of the first surface.

6. The semiconductor device of claim 5, wherein an electrical connection with the second portion of the first surface surrounds the first portion of the first surface.

7. The semiconductor device of claim 1, wherein the semiconductor package comprises a cavity configured to receive a portion of the third lead.

8. The semiconductor of claim 7, wherein the third lead comprises a surface that slidingly fits within an inner wall of the semiconductor package, and wherein the inner wall defines a portion of the cavity.

9. The semiconductor device of claim 1, further comprising a conductive material that passes through the non-conductive material to electrically connect the second lead with the second portion of the first surface of the semiconductor package.

10. The semiconductor device of claim 1, wherein the semiconductor package is hermetically sealed within the volume.

11. The semiconductor device of claim 1, wherein the first lead comprises a pedestal, and wherein the semiconductor further comprises an isolation ring that surrounds at least a portion of the pedestal.

12. The semiconductor device of claim 11, wherein the non-conductive material is adjacent to the isolation ring.

13. The semiconductor device of claim 1, wherein the electrical connections between the first lead and the semiconductor package, the second lead and the semiconductor package, and the third lead and the semiconductor package do not comprise wire connections.

14. A semiconductor device comprising:

a semiconductor package including a plurality of transistors, wherein each transistor of the plurality of transistors has a gate, a drain region, and a source region;

a first lead, a second lead, and a third lead, wherein the semiconductor package and the second lead are located between the first lead and the third lead; and

a non-conductive material surrounding the semiconductor package, wherein the semiconductor package is within a sealed volume defined at least in part by the first lead, the third lead, and the non-conductive material.

15. The semiconductor device of claim 14, wherein the first lead is electrically connected to a first pad of the semiconductor package, wherein the second lead is electrically connected to a second pad of the semiconductor package, and wherein the third lead is electrically connected to a third pad of the semiconductor package.

16. The semiconductor of claim 15, wherein the electrical connection between the first lead and the semiconductor package and the electrical connection between the second lead and the semiconductor package mechanically couple the first lead to the semiconductor package and the second lead to the semiconductor package.

17. The semiconductor of claim 15, wherein the electrical connection between the first lead and the semiconductor package and the electrical connection between the second lead and the semiconductor package thermally couple the first lead to the semiconductor package and the second lead to the semiconductor package to draw heat from the semiconductor package.

18. A method comprising:

electrically connecting a first lead to a first portion of a first surface of a semiconductor package, wherein the semiconductor package comprises a plurality of transistors, and wherein each transistor of the plurality of transistors has a gate, a drain region, and a source region;

electrically connecting a second lead to a second portion of the first surface of the semiconductor package;

electrically connecting a third lead to a second surface of the semiconductor package;

surrounding the semiconductor package with a non-conductive material; and

sealing the semiconductor package within a volume defined, at least in part, by the first lead, the third lead, and the non-conductive material.

19. The method of claim 18, wherein said electrically connecting a third lead to a second surface of the semiconductor package comprises sliding a surface of the third lead along an inner wall of the semiconductor package, and wherein the inner wall of the semiconductor package defines at least a portion of a cavity.

20. The method of claim 18, further comprising:

forming a conductive pedestal on the first lead; and

surrounding the conductive pedestal with a non-conductive isolation ring.